specter and friends showed us, again, that "security" is a fantasy.
I would not expect anything different from RISC-V CPU designs.
BTW, are specter and friends fixed in Zen4?
I would not expect anything different from RISC-V CPU designs.
BTW, are specter and friends fixed in Zen4?
Look into `fence.t` [0].
0. https://youtu.be/C3nOjXhyPfk?list=PLtoQeavghzr3atxNQig-sLGbw...
Like everything, it comes with trade-offs, and here some ISA design choices come straight from the experience accumulated on advanced CPU design. For instance, if I did understand well, the handling of arithmetics flags in RISC-V is what it is because of it makes out-of-order CPU design way easier.