ARM (and the mobile market) will crush Intel. Intel is seriously late to the game here, and never took performace/watt seriously for decades, and ARM is going to disrupt them hard.
I am fairly sure that the same thing will now happen with x86 and ARM -- it just depends on the timeline.
Today, the story is very different. Apple can produce its own SoC designs, as with the A5, or even produce its own ARM _core_ designs, like Qualcomm does, or it can buy from one of a number of healthy vendors who show no signs of quitting ARM anytime soon. If this Intel core had a genuine dramatic performance advantage over the A15 (which it will be competing with, given the timescales), at the same power usage, that would be one thing, but that's far from clear right now.
Things are much different now. Intel chips are faster than ARM, of course, but they are also vastly more power hungry. Power consumption matters more than speed in most devices these days (otherwise Intel would already be in everybody's phone) and will likely continue to do so for a long time. Intel shows no sign of being able to reduce their power consumption to the level needed while still retaining decent speed, whereas ARM shows every sign of being able to keep increasing their speeds while keeping power consumption where it needs to be.
http://www.anandtech.com/show/5365/intels-medfield-atom-z246...
http://datasheet.digchip.com/205/205-00367-0-970.pdf gives typical power dissipation as 42W @1.8 GHz, 1.3v
For a later design, http://datasheets.chipdb.org/IBM/PowerPC/970/PowerPC-970FX.p..., section 3.1.5 gives 60W for the 2.2 GHz version at 105 degrees Celsius.
http://en.wikipedia.org/wiki/List_of_Intel_Pentium_4_micropr... gives comparable values for the TDP for 2002-era Pentiums.
I get the impression that IBM's data is real max (but 'Maximum power at 85 C is the ONLY value that is guaranteed by Manufacturing Test.'), while TDP may be lower than max (Reading http://en.wikipedia.org/wiki/Thermal_Design_Power)
Or am I overlooking a factor for #CPUs?
I always thought the water cooling was either an effort to decrease noise or over engineering or preparation for more cores and/or more speed (either of which were a necessity to keep up with Intel chips).
I don't have hard data, but as far as I know, once Macs went Intel, they all got significantly faster and cooler.
This was most visible at the top of the line. The last Power Mac G5 had the liquid cooling system and the top end ran four cores at 2.5GHz. I don't know about the liquid cooled model in particular, but the G5s in general were notorious for being noisy due to fans.
The first Mac Pro which replaced it ran 8 cores at 3.0GHz and was known to be astonishingly silent. I personally used one as my main work computer for years and it was impossible to get the fans to run fast enough to be audible unless you disabled the smart controls by e.g. leaving a kernel panic on the screen for a while. Obviously, this could be due to more advanced thermal design as well, but even allowing for that, you have twice as many cores, running at a higher clock rate, vastly faster in most real-world use, and with a much simpler cooling system.
The laptops had a similar story. The PowerBook G4s would get astonishingly hot, while the MacBooks were much less bad (although still not great initially).
How many times have we seen Intel announce a hardware partnership with a company (especially in mobile) that ultimately went nowhere? I think this comes down to, I'll believe it when I see the devices shipping.
* ARM's big.LITTLE promises to drastically reduce power consumption under low CPU load. It seems unlikely Intel will be able to offer something similar anytime soon.
* If you compare Atom Z2460 with SoCs based on Cortex-A15 (both are supposed to start selling by the end of the year), it doesn't look that well.
Price will definitely be important, but judging by how hard Intel is coming into this segment, I can only assume that it's willing to match or get very close to ARM component costs.
Intel's chips are internally RISC, with the only overhead of decoding and fusing the ops and the transistors to do this. And despite this overhead, they're still miles ahead.
The only argument left then is the actual instruction sets at asm level, and here, CISC has an advantage, because they can do so much more in one instruction (take memory addressing modes for example), so they're more compact from an executable point-of-view and instruction cache point-of-view.
I wonder how much of an x86 chip is dedicated to handling legacy instructions or largely unnecessary instructions. How much saving could be achieved by a radically simpler instruction set (for example no neg/call/ret/push/pop/bcd instructions). If you look at the http://en.wikipedia.org/wiki/X86_instruction_listings then most of the instructions seem unnecessary. Does anybody have some information about this?
It's been a long time since I was in a closely related biz, but back then, the answer was "not much if you want to go fast".
Instruction decode isn't a huge deal. Micro-op sequencing isn't a big deal if you're going out of order (and many risc instructions tend to get broken into micro-ops).
The number of architectural registers used to be a big thing, but X86_64 is good enough. (I don't know if anyone got around to renaming memory.)
Instruction decode isn't really difficult - 4-way decode could arguably be called difficult, but there's not much of that.
Intel does waste lots of chip real estate on caching big instructions (http://www.anandtech.com/show/3922/intels-sandy-bridge-archi...) and on wide decoders that fault and go to microcode when they encounter some instructions. Think of how inefficient the SSE and AVX encodings are, because the need to escape 8086 code. Or the extra byte needed to access the extra 64bit registers. New CPUs are seldom limited by decoder width on regular code but it does cost watts and it costs space that could have been used for cache or for making the chip cheaper.
I'm not even sure ARM is the best ISA. It doesn't matter which alternative is the best: I just predict that the best won't win because Intel will use their superiority in manufacturing to artificially boost the success of their lackluster CPU design guys.
Intel's 65nm (Pentium M) can still beat similarly clocked (1.5 Ghz) ARMs at 28nm - that's not due to process, that's due to a much more powerful architecture designed for speed over power consumption (Pentium M, then Core, Core 2).
The instructions that fault are the very rarely used ones like weird string processing ones. Those are not going to be used in the middle of number-crunching loops.
Escaping float ops hasn't been needed since the 486 days, so I'm not sure what on earth you're talking about.
Intel's branch predicting and memory / cache pre-fetching are the best in the business. To say their CPUs are "lackluster CPU design", is pretty ridiculous, despite Atom being pretty crap.
You can only compare chips that have the same power consumption. A 1w chip against a 45w (or whatever) chip is not a comparison you can make.
Specifically, Intel now demonstrates a Penwell SoC with a Saltwell (Atom) core made on Intel's 32nm LP process and it benchmarks well against Cortex-A9 chips made on TSMC's 40nm process. I said that I guess that if Intel manufactured an ARM chip on Intel's 32nm LP process with the same die area and power consumption as their x86 chip, the ARM chip would be preferable. Like Anand said, We'll see how this SoC stacks up against multi-core Cortex-A15 chips on TSMC's 28nm process.
If Intel changes the priority and makes their Low Power process transform to the next node together with (instead of after) the high-performance process (currently one step ahead at 22nm), then they will be seriously ahead of whoever manufactures ARM chips (TSMC and others).
> The instructions that fault are the very rarely used ones
They complicate the decoders and take up space and I think take up latency (clocks) during decoding. This costs money even when these instructions are not used.
> Escaping ... so I'm not sure what on earth you're talking about
REX prefix: http://www.x86-64.org/documentation/assembly.html
> To say their CPUs are "lackluster CPU design", is pretty ridiculous
Their power efficient design is in-order and pretty crap. You should read what Linus Torvalds had to say about it. Yes, Conroe was awesome and Sandy Bridge is awesome, but that is not what we're talking about here.
Yes, Intel is usually the first to bring a new process online (and their 22nm Ivy Bridge is due to ship in a few months), but for the entire history of the Atom product line, Intel has failed to make use of their fab advantage. They probably never will, so long as it is more profitable to put the desktop/laptop/server product lines on a new process first.
One can imagine that big L2 caches, high memory bandwidth and eventually 64-bit addressing will be important for mobile devices. On one hand Intel can attempt to drive existing high performance x86 solutions to low power, and on the other hand ARM can attempt to extend their architecture for high performance - given more transistors and better power characteristics available to both sides, the rest of the world lagging Intel.