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Comment by kllrnohj | Hacker News Reader

Or buy an X3D that's homogeneous, like the 5800X3D or upcoming 7800X3D.

I have no idea why AMD made the 7950X3D be this weird 50/50 split. Why not make both CCDs have 3D V-cache and make it the true halo part it should be? Then cut costs with the 7900X3D?

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The added cache isn't free; the CCD with vcache runs at a significantly lower clock speed. If every task was always put on the most appropriate CCD, the heterogeneous approach is pretty much a direct advantage, as frequency-sensitive workloads get high frequencies and cache-sensitive workloads get lots of cache.

Whether it will ever get good enough at picking CCD remains to be seen though.

Perhaps but I have no idea how any scheduler can possibly figure out if a workload is frequency or cache sensitive. The current strategy seems to be "if game, use cache, else use frequency" and it sorta works OK-ish? Although then there's games that aren't detected right (like Factorio) and it's then a terrible result.

But if you look at single threaded results with it set to "prefer cache" it's not really that much slower. Yes you'd have a flagship with lower single-threaded Cinebench results, but I mean that also happens with pretty much every HEDT platform and nobody bats an eye at that. The results are still a significant step beyond the 5000 series single core results.

There was some outcry about 5800X3D having lower clocks. This was there "we solved the clock speed problem with a v-cache SKU" move, which was promised somewhere... And I guess, if you use games as a primary load and they fix their scheduler, then it seems to work for both cases.

But I don't like this franken chip. I would much rather 7800X3D. But then, I don't play games, so the scheduler would just be terrible.

Because the added 3D V-cache increases heat. That's also why the X3D variants have lower clocks than the non-X3D versions. Two CCDs with V-cache is apparently too hot.

Previously that wasn't the issue, the issue (according to AMD) was that there was a huge interchip communication bottleneck with the extra L3 on both chips.

If thats fixed, then AMD is just being cheap :P

epyc has v-cache on every die on -X skus, doesn't it? it's fine

https://www.anandtech.com/show/17323/amd-releases-milan-x-cp...

> Critically, AMD has opted to equip all of their new V-cache EPYC chips with the maximum 768 MB of L3 cache, which in turn means all 8 CCDs must be present, from the top SKU (EPYC 7773X) to the bottom SKU (EPYC 7373X). Instead, AMD will be varying the number of CPU cores enabled in each CCD.

(unff 768MB of cache)

afaik AMD has said the voltage is one limit because they share a voltage rail, so, you can't go outside the operating limits of the v-cache die. But thermals are another because the cache die does limit thermal transfer out of the CCD as well. They did shave it down (to maintain package height) which helps somewhat but I think it does run at least a bit hotter due to the separation between dies. But voltage is, afaik, the primary limitation, and I've never heard of cache coherency as being the problem.

I don't think they're lying about the cache die hurting clocks, that's obviously true from 5800X vs 5800X3D and lower clocks hurts performance in some applications, so they're legitimately trying to offer the best all-around-performer they can as a general-purpose CPU. But I also think they're being very careful about how much they let Ryzen cannibalize their Epyc X3D lineup too, and doing their best to salami-slice this into multiple releases.

There's no reason they couldn't have done 5900X3D last gen, and I bet eventually we will see a dual-cache-die release too. There is (based on Epyc) pretty obviously no technical limitation here, they just don't want to sell it to you right now. You can make excuses like "oh the market just isn't there" but... I think they will do it eventually. For now they are just using it to distinguish between Ryzen and Epyc, previously it was if you wanted >8 cores, now it is 12C and 16C but only one cache die, in a gen or three they will throw in the towel and let you buy all-cache-die configs if that's what you want.

They very specifically said it was an interconnect issue. With the extra L3, adjacent dies made so many requests to each other's cache that it turned into a bottleneck, and this wasnt an issue on Milan X because its IO die is apparently beefier.

I cant find the source because I am on mobile and now google search is flooded with X3D chatter :/

interesting, if you can find it in your history let me know!

That doesn't pass a sniff test at all. The 7950X3D TDP is 120W vs. the 7950X's 170W, even ignoring that modern TDP is a dumb metric actual power consumption also backs that up - the 7950X3D uses signiifcantly less power than a 7950X. And, as an expected result of that, the 7950X3D also runs cooler as a result than the 7950X does. There's no evidence to support a thermal or power limit here.

And it wasn't that different for the 5800X vs. 5800X3D, either. The extra cache at the same TDP seems to translate to around a 200mhz clock speed loss, temperatures otherwise the ~same.

Cache is also not very power hungry in general. Perhaps you meant it was a thermal barrier but again see above - all evidence points to AMD having figured that part out, there's no hint of thermal constraints on either the previous nor current 3d v-cache parts.

So they can sell us a 7990X3D 6 months down the line for $1000

Does AMD have a history of this blatant of a move? That would be an Nvidia level of arrogance.

They are no longer the underdog, I would expect behavior parity with the other semiconductor vendors.

In this case it more depends on what Intel does. If Intel somehow beats this before Zen 5 is ready I don't see why not. AMD has these all cores with v-cache parts available on its EPYC lineup so it is technically possible. (not yet with Zen 4 but Zen 3 parts do exist)

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