It is also covered in the ISPD'22 paper, "Scalability and Generalization of Circuit Training for Chip Floorplanning", by Summer Yue, Ebrahim M. Songhori, Joe Wenjie Jiang, Toby Boyd, Anna Goldie, Azalia Mirhoseini, and Sergio Guadarrama, which was written by authors from the Nature paper. https://dl.acm.org/doi/pdf/10.1145/3505170.3511478
In their ISPD'22 paper, link above, Figure 7 shows a 5x speedup but 0.3% worse placement results with pre-training on diverse designs vs. running from scratch. Pre-training on previous versions of the same design does improve results by 1.7% vs. running from scratch, and has similar runtime benefit to pre-training with diverse designs. Given that the Circuit Training approach requires 41x to 646x wall time and an even higher factor of compute time vs. other standard techniques, the 5x speedup with pre-training is insufficient to close that very large gap. Furthermore, pre-training does not improve results vs. training from scratch, unless you are pre-training on previous versions of the same design but even then a 1.7% improvement in the circuit training results is not adequate to demonstrate improvement vs. standard techniques as can be seen by examining the results from Professor Kahng's group's work.
This concern about pre-training has been answered in multiple forums, including the discussion in ISPD'23 Session 8, when Mr. Washauer-Baker raised the same issue. It's unfortunate to see Gabriel Warshauer-Baker, Anna Goldie's spouse, making repeated personal attacks on Professor Kahng. Please focus on the scientific discussion.