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Comment by usr1106 | Hacker News Reader

Use the cache as RAM. So I guess you could run a small Linux system just in cache without any RAM?

Why? As a fun project with some old motherboard for example :)

With the some of the new AMD Epyc CPUs having over 1GB of L3 cache, you could run a pretty full-featured Linux distro + app entirely in cache.

If anyone can verify that Cache as RAM actually works on AMD though or explain how AMD boots without it that would be great:

>Cache-as-RAM (CAR) is no longer a supportable feature in AMD hardware.

https://git.furworks.de/coreboot-mirror/coreboot/commit/a245...

The PSP sets up the memory controller before the x86 cores are started. It's not implausible that the PSP has some sort of cache as RAM stage, but that's before Coreboot starts.

For a moment I was confused that the PlayStation Portable would have x86 cores.

With a fair bit of effort; notably, DMA and IOMMUs probably won't work, and most modern devices don't really support PIO. You might be able to boot a really simple environment that runs out of an initramfs though. It's also entirely not obvious to what degree you can use the paging system.

It'd likely be a substantial effort to port Linux.

Sure, I would not expect to do any advanced IO. But right, probably there is no serial console really close to the CPU either, this is not a Raspberry PI. No idea what signals could be used for that.

Page tables I am not sure either. Could you still do it like in Linux 1.0? No idea what things looked like then, but I assume much less dedicated hardware support.

> probably there is no serial console really close to the CPU either

outb to 0x3f8 might work.

I know there were once versions of Linux that supported running without an MMU. Those versions, with very limited hardware support, might work in this mode.

It's still part of the kernel code: https://www.kernel.org/doc/Documentation/nommu-mmap.txt

And apparently, good enough to run DOOM: https://hackaday.com/2022/12/07/a-tiny-risc-v-emulator-runs-...

Hasn't Intel supported DMA into L3 cache for something like a decade now?

Right, I did not specify what L ;) And the original article did not mention either.

It is supported on true Xeon systems.

I believe that it is not supported in Core CPUs, not even in those of them which were branded as Xeon E or Xeon W.

Substantial effort I don't doubt. First probably years of learning how things work under the hood for most normal mortals.

DMA on x86 does update contents of CPU caches.

Yes, it does, but that doesn't mean the hardware necessarily supports doing it without a memory controller.

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