Ofc, worldwide royalty free is not enough (or just be allowed to implement the ISA...), silicium is really about performance, and I sincerely hope RISC-V will end up providing microarchitectures (open or not) "good enough" to do the job.
I am perfectly aware RISC-V will fail if not providing at scale really good implementations. Rumors say "really performant" implementations are not expected before 2024.
The problem with this argument is that it ignores the cost of creating the microarchitecture. It’s almost certainly cheaper to license an Arm A series core than to create a comparable RISC-V core from scratch.
Sure we have a firm like SiFive that licenses RV cores to third parties but the existence of firms like Arm and SFive shouldn’t be taken for granted. If rumour has it SiFive were almost taken over by Intel. Thankfully Nvidia were stopped from buying Arm.
If you wish for Arm’s demise you may get the end of their business model and that probably isn’t a great outcome.
But I agree that without _REALLY_ performant implementations, risc-v WILL fail and rumors say that things won't start to get serious before 2024. Nevertheless, in its current state, failure is still a more than valid outcome.
What is interesting imho is that they WILL get serious by 2024, including P670, Veyron, Ascalon. All of them seem to implement RVA22 + ratified V.
This is a very fast timeline for RISC-V, which privileged spec was only ratified in 2019.
It all has been happening much faster than even the most optimistic estimates were.
As far as I know and specs wise, RISC-V has been kind of ready for a while, only missing very high performance implementations.
My first real risc-v target is a 100% RV64 assembly keyboard firmware though. Looking at mango pi pro mq boards, but I wish we had 'smaller' RV64 GPIO/USB boards for that, maybe a small GPIO/USB board with a USB block+FPGA with enough gates to instance a small RV64 core.
These are known "detonators" set up for next year. There's more we don't even know of. It is going to happen.
RISC-V is inevitable.
>As far as I know and specs wise
December 2021's batch of extensions done the magic. No hardware out there implements them.
Once it arrives (e.g. Veyron and Ascalon), the thorough disruption of the whole CPU landscape, from microcontrollers to supercomputers, starts.
The acceleration and massive momentum that we've seen to date is nothing compared to what's to come.
I want to share you optimism, but I advise you to keep your cool. There is a long road to reach the performance of x86/arm microarchitectures (it is harder for risc-v since the "market is over saturated"). And those performant implementations must get access to the best silicium node process... and that...
Veyron's supposed to have actual server boards on sale late this year.
Ascalon, CPU chiplets and a full AI accelerator product using them, succeeding their current one, which iirc uses SiFive IP.
> non-toxic IP cores with enough performance from RISC-V
Why would anyone also their designs to be used for free or for cheaper than ARM does?
I don’t see how can high-end/competitive RISC-V cores could be fully open/free and without that how is it better than ARM.
arm and x86 are not royalty free ISAs, RISC-V is, then RISC-V is mechanically a better choice, until it does a good enough job.
Only ARM can license ARM cores to others.
Using RISC-V, any company who can design their own cores can also offer them for licensing.
There's already tens of companies offering hundreds of cores for licensing.
This is much better than ISA-enforced vendor lock-in, which is the situation with x86 and ARM.
And the companies that don’t want to make it their core business but can afford enough resources (e.g. Google, Apple, Amazon) would just use them to leverage their core products.
I could only see this on the lower end where margins/required R&D investment are relatively low.