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Yes, it totally counts and is indeed being vertically stacked on Ryzen products today. Cache takes up a huge portion of total die area and doesn’t hurt temperatures too much.

For now, AMD is using the technique to add more cache to their CPUs rather than moving all of it to another layer.

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As I understand it, this is because the 3d stacking is fairly expensive (it adds a lot of silicon and extra manufacturing cost), so 3d cache only makes sense once your chip is too big to put all the cache in 2D.

I suspect there is a yield issue also. that is one large chip with one defect in the wrong place is just glass. with chipsets you would assemble the module after chipset unit test.

but maybe redundancy and binning has made this moot.

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