The spurious UART interrupts mentioned in the article are probably related to a "feature" of the DesignWare UART component used in the JH7110 SoC.

When trying to write the UART's LCR (line control register) when the UART is busy, a BUSY interrupt is generated. If this is not handled, the UART will continue to generate an interrupt storm.

The Allwinner D1 RISC V SoC (and several other ARM-based Allwinner chip) also uses the DesignWare UART and suffers from the same problem.

See the Linux driver source for a workaround:

https://elixir.bootlin.com/linux/latest/source/drivers/tty/s...