Andrew Waterman (Chief Engineer, Co-Founder of RISC-V and SiFive) describes the motivation for a new instruction set for RISC V in "Design of the RISC-V Instruction Set Architecture" (https://people.eecs.berkeley.edu/~krste/papers/EECS-2016-1.p...).

The document contains a short discussion of the pros and cons of most architectures which were still somewhat popular at the time RISC V was designed (the Power/PPC is omitted) - MIPS, SPARC, Alpha, ARMv7/v8, OpenRISC and x86.

Major points that count against SPARC in Waterman's view are:

- SPARC register windows have significant power and area cost and complicate superscalar implementations

- Branches use condition codes which result in more complexity for OOO implementations with register renaming

- Load/store pair instructions also complicate implementations with register renaming (ARMv8 has introduced those, too)

- Moves between the floating-point and integer register files must use the memory system as an intermediary

- The only atomic memory operation is fetch-and-store, which is insufficient to implement many wait-free data structures

The openly available SPARC implementations are either embedded-style cores (e.g. Gaisler's LEON3) or relatively specialized cores for highly parallel workloads such as web serving (T1 and T2). Regular Sun 4m/4u cores were not available in source form, but the SPARC license would have allowed alternative implementations. The license used to be available for a one-time fee of $99, but it seems SPARC can be used free and without royalties now, the $99 are an optional registration fee at SPARC International (https://sparc.org/faq/#q3).