ISA complexity breeds microarchitecture bugs.
In the internet era, x86 is an anachronism.
RISC is the way forward.
RISC-V is inevitable.
In the internet era, x86 is an anachronism.
RISC is the way forward.
RISC-V is inevitable.
I understand you're trying to argue against my main point, which is:
>ISA complexity breeds microarchitecture bugs.
And definitely stands.
From there I have no idea how you derived that bugs are impossible under a simple ISA, which is implied in your statement.
As an added note: ARM in particular isn't simple. It's simpler than x86, but that's a low bar to meet.
>even if you weren’t wrong, it would be off-topic
We will have to agree to disagree on this.
I mean, sure. On many levels and planes you are correct, but not where any of the intersections matter.
I am talking about RISC architectures such as RISC-V (which I mentioned by name), the sort that can scale all the way up to supercomputers and down to microcontrollers.
There is no justification for putting up with x86's complexity. This complexity has negative consequences such as vastly increased likeliness of micro-architectural bugs.
It is utter madness for many of its current popular uses, such as in servers handling personal data.
When a CPU implements speculative execution, this class of attack becomes a concern. If it doesn’t, it’ll be too slow for most applications. Fortunately, the people who are - unlike you - actually helping RISC-V are working on efficient countermeasures: