Comment by segfaultbuserr | Hacker News Reader

Comment by segfaultbuserr | Hacker News Reader

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> and maybe an EEPROM or two as a poor man's PLD for certain kinds of combinatory logic.

The entire ALU and Control Unit of the CPU are programmed in EEPROMs. The ALU uses 7 ROMs [1], the Control Unit uses 3 ROMs [2], the program counter uses 5 ROMs [3], the bit shifter uses another ROM [4], so I see 16 EEPROMs in total. Thus, hundreds if not thousands of logic gates are replaced by bitstreams in EEPROMs. This CPU certainly is based on the design philosophy of "EEPROMs as poor-man's FPGA" (not meant to be interpreted in a discouraging way, I found this design is still rather interesting).

[1] https://github.com/pineapple-one/hardware-eagle/blob/main/al...

[2] https://github.com/pineapple-one/hardware-eagle/blob/main/co...

[3] https://github.com/pineapple-one/hardware-eagle/blob/main/pr...

[4] https://github.com/pineapple-one/hardware-eagle/blob/main/sh...

Yeah that is cool, because I hear that the tooling for FPGAs is still very proprietary. And it doesn't do much good if one's CPU is "Click the CPU button on the FPGA GUI"

EEPROMS, I assume, you can build your own programmer pretty easily?

> EEPROMS, I assume, you can build your own programmer pretty easily?

Programming a EEPROM by bitbanging it from a microcontroller is a basic programming exercise. First, send a special unlock sequence according to the datasheet (usually with a lot of 0x55 0xAA). Next, put all the address bits on the address lines, strobe that in via a control line. Finally, put all the data bits on the data lines, strobe that in via a control line. You only need around 100 lines of code to create a basic programmer (although making a universal one capable of programming all existing models on the market would be non-trivial, as it requires a massive look-up table similar to the one in "flashrom").

PALs & GALs are also relatively simple components programmable using non-proprietary hw & sw.

There are some FPGA families supported by fully open source toolchain today.

And there's CPLDs, which fall in between complexity wise.

Any of those would offer much shorter propagation delays (read: higher clocks) than EEPROMs.

I recently contemplated using a CPLD for a project and discovered that (at least the ones I was able to find suppliers and documentation for) are even less open source friendly than FPGAs are, none of the CPLDs I found seemed to have any open source tooling that I could find.

I would love to be corrected on this because other than proprietary tooling that only supports windows … a CPLD seemed perfect for this project.

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