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Comment by snvzz | Hacker News Reader

Hopefully RISC-V will take off in high performance, before any of this is relevant.

riscv is just an instruction set. in a lot of ways its not as nice as AArch64 or x64. I don't see a strong impediment to having a world-class riscv processor, but it hasn't happened yet and the only reason to pick riscv vs arm is that you're a bottom-feeder, don't want to pay arm licensing fees. People who will switch architectures to save a few cents aren't people who make or buy world-class cpus.

I think you've just convinced me that RISC V is the way to go, long term.

Historically, bottom feeders won in IT. unix was a bottom feeder againts the IBM os'es and VMS. x86 was a bottom feeder architecture against mainframes, server class hardware, and workstations. Linux was a bottom feeder against the real UNIXes like SunOS and HPUX.

Bottom feeders get picked as cheapest option, then client demand of better features slowly pushes them upwards. Meanwhile the top concentrates on its most profitable customers, showing disdain for bottom feeders until they've grown out of control.

The last 5 Tandem owners are probably still out there somewhere, showing all of us what real uptimes look like.

Even if it does, this is also highly relevant to desktop CPUs.

>highly relevant

It is a SIMD extension, despite Vector era (RISC-V Vector 1.0, ARM SVE2). Far from relevant.

>desktop CPUs

Will too be RISC-V. Not far from now.

Some chips (likely from Intel and AMD) will offer "x86 acceleration" to run legacy software, for a transitional period lasting a few years.

Before making bold claims, it might be useful to get more familiar with a mess that are myriad of RISC-V extensions and seemingly insane/backwards decisions it makes completely ignoring the hard lessons learned by both ARM and x86.

>it might be useful to get more familiar with a mess that are myriad of RISC-V extensions and seemingly insane/backwards decisions it makes completely ignoring the hard lessons learned by both ARM and x86.

FUD unless you give specific examples and evidence backing them.

Many "seemingly insane/backwards decisions" in RISC-V are good decisions backed by large bodies of data.

Refer to Computer Architecture: A Quantitative Approach[0].

0. ISBN-13 978-0128119051

Previously: https://news.ycombinator.com/item?id=32053592

Somebody disagreeing with RISC-V design, news at 11h.

Just wait for RISC-VI, it'll be great

Judging by the PC's history of transitioning from 32-bit to 64-bit x86 (still not complete after 20 years), and from x86 to ARM (Windows on ARM is at 14% market share after more than 10 years)… well. I'm just a bit skeptical.

Though to be fair, it all depends on the hardware. Windows on ARM struggled not just because it wasn't x86 but because nobody was making powerful-enough ARM processors. Now that those processors are starting to arrive, it's supposedly going to take off in the next few years. …Probably only on the low end, though. But you never know.

And RISC-V? Maybe someday.

>(Windows on ARM is at 14% market share after more than 10 years)

Is it really that high? Where do these figures come from?

According to that research https://www.counterpointresearch.com/insights/arm-based-pcs-... 14% of laptops currently being sold have an ARM CPUs.

However, 90% of them are Macbooks, which means the share of the ARM laptops which run Windows, Linux or ChromeOS is 1.4%.

I don't think Win ARM market share is at 14%. Where did you get that stat?

For SIMD kernels that do "general-purpose computation" like formatting strings, parsing documents, or entropy encoding and decoding, it's difficult to use variable-length vector extensions, and ultimately these sorts of things written for these targets are likely to branch at runtime based on the actual width reported by the CPU. One of the most important operations for this sort of thing, TBLQ, doesn't even exist in SVE prior to SVE2.1 published ~1 year ago, so parser devs targeting aarch64 can safely target NEON until SVE2.1 lands in the hardware they care about.

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