New BeagleV single board computer adopts Microchip's PolarFire SoC with FPGA
linuxgizmos.com
linuxgizmos.com
The big FPGA players have mostly quit that shit; AMD/Xilinx, Intel/Altera/Whatever dumb name its about to be spun back out as, and Lattice all have free versions of their dev tools for at least their parts small players can afford. They just want you to buy chips and IP.
I haven't heard of the Yosis folks making a PolarFire backend, so I don't think there's an open alternative.
Libero is even FlexLM based licensing like the bad old days of proprietary dev tools.
When searching for hardware part numbers, you should first omit the letters at the end, and then read carefully about what they mean.
Then click on the link "Libero license selector guide" to download the Excel spreadsheet. Filter or search for MPFS025.
Microchip does Excel spreadsheet selector guides for everything. As a general guideline when dealing with hardware components, don't trust anything you read on a web page.
At least when you buy Vivado and Quartus you can actually keep using it...
They had announced this board sometime ago with totally different specs (https://old.beagleboard.org/static/beagleV/beagleV.html).
That being said, I'm actually looking forward to this board. I see this as kind of an alternative to the Xilinx Zynq boards.
Microsemi (now Microchip) does not really cater to the low-price hobbyist market. A lot of their sales are high-reliability FPGAs and weird things like anti-fuse FPGAs (one-time programmable). I will say that they were very early adopters of RISC-V. We've been using their core in our product for something like 5 years now.
I suppose the bigger news is that this is a RISC-V device with some FPGA fun mixed in.
In high-level languages you got functions, variables and scopes while in assembly you need to build them yourself using more primitive units, i.e. instructions and registers.
In assembly you got many helpful instructions and easy memory access while in FPGAs and ASICs you have... nothing. Only wires and boolean logic.
It allows you to build some things extremely efficiently, e.g.: Press button 1 and 2 to activate LED 1. No clocks, no memory accesses, no I/O polling or interrupts, just a direct connection from some inputs to others with some logic in between.
Although there are many modern tools, libraries and IP blocks to make FPGA programming easier or even possible with languages like Scala or C++, it usually takes way more time to build anything compared to doing it with the help of a CPU.
This seems like a mad science. Is there a recommended entry point like a book or learning resource?
The only exposure I have is from the FPGA stereo disparity module on the Mars Rover. And sadly I left before I could really pick any brains. Or ASIC Bitcoin mining.
FPGAs usually clock much lower than CPUs. If you want to beat a modern multicore CPU running at 5GHz with a 100MHz FPGA, you need to do a lot more per cycle to win. Your optimal problem is either highly parallel or solvable using a deep pipeline that gives you crazy throughput.
Since accessing external RAM is much more complicated on a FPGA and you don't have all the nice prefetching and caching levels of a CPU, you better make do with the limited on-board memory.
Usually this limits you to real-time stream processing like audio, video, packet filtering or I/O muxing.
But if you have an interesting problem in these spaces, FPGAs can be crazy power efficient and fun.
At my university, we used a ZynqBerry (Raspberry Pi format and only around $100) with the Vivado tools, so maybe that would be a good start for you as well.
https://www.waterstones.com/book/digital-design-and-computer...
There is this new book: https://nostarch.com/gettingstartedwithfpgas
It's great for stuff like driving LED matrixes, offloading crypto operations, or signal processing. Anywhere you want low latency, but simple processing.
HDLs have familiar syntax that makes it seem like you can just program algorithms imperatively (for loops, if statements, functions etc) but it's all just a mean trick to catch software people out, and generally won't give the results you expect.
On top there's then the fact everything happens at the same time, the faff of making everything synchronised and making sure it meets timing and fighting the frankly awful tooling every step of the way.
Once you get it, it's fine, but you have to unlearn a lot of software muscle memory and keep the actual design work (boxes and lines) almost entirely separate from the implementation (typing your boxes and lines into a text editor).
The biggest issues are really:
1. The tooling is generally awful. Open source tooling is very primitive and not usable. Commercial tooling is unaffordable to hobbyists. There are a couple of exceptions:
a) Vivado which I haven't used extensively but seems fairly nice. Unfortunately the FPGAs it works with are not cheap.
b) I discovered that Intel provides a free version of ModelSim. I've used Questa a lot (the "pro" version of ModelSim more or less; their branding is confusing) and it's great.
It also doesn't help that all the tools use TCL which is also awful.
2. SystemVerilog is just a really bad, ancient language. It wasn't even designed for synthesising ASICs, let alone FPGAs! You're writing a simulation of an ASIC, and then some other tool tries to infer how it should run that simulation on an FPGA. It's a completely bonkers system.
It's not just the system that is bonkers. The language is too. Implicit casts all over the place, undefined values as part of the language (though not in Verilator!), multiple assignment types, ridiculously flexible array indexing.
Maybe VHDL is better... but unfortunately SystemVerilog won the language war in the ASIC space so that's what I know.
It also doesn't seem like we'll get a replacement any time soon. You'd need buy-in from the big vendors otherwise debugging will always be a total nightmare.
Though it would be nice if there was something like Typescript for SystemVerilog - something that fixed all the very rough edges and footguns but didn't change the code so much that debugging is painful.
Maybe you're working off old information, but the FOSS tooling (ghdl, yosys, nextpnr) is completely sufficient for hobbyists. If you're doing huge, high-speed designs on expensive FPGAs, sure, use the vendor tools, but for your average iCE40/ECP5-scale design, FOSS is the way to go.
Maybe in time they'll move on from the "here's a bunch of random poorly documented tools, you only have to do all of the integration work!" stage, but they aren't there yet.
The hard parts are...
a) the "fuzzy" bits -- timing, propagation delays, etc. the tool will warn you about it but it's not always easy to understand. It's easy to end up with a mess that makes perfect sense "logically" and works in your sim, etc. but actually only sorta works in meatspace.
b) the tools. They all want to ram you into their shitty 1000lb IDEs which are forks of Eclipse from 15 years ago with a heaping dose of Tcl on the side and only work in some specific version of RedHat or whatever. Forget about using your preferred editor or IDE or build tool, they want to ram you through their GUI. You can sometimes route around it, by reverse engineering their Tcl and figuring out what command line invocations rae actually happening behind the heap of wizards they want to herd you through... but you'll always end up back in Quartus or whatever at some point. HW Engineers seem to be suckers for this kind of punishment.
With typical programming, you're describing software. With VHDL / Verilog, you're describing hardware. When Verilog/VHDL "runs", its just the hardware existing, ready to react to whatever happens later. There's no code that "steps" through if-statements or loops... there's instead state-machines that get stored into memory... with their outputs being directed upon physical wires you name.
As far as a "language" goes, I'd say its close to C++ Template Metaprogramming, though the syntax is very different. But the concepts are surprisingly close. C++ Templates do not compile into code, they compile into concepts and layouts... so to speak.
Well, of course C++ Templates eventually turn into C++ code. But imagine if the end result were flipflops, wires, and 1-bit memory instead. Maybe I'm describing it wrong... or maybe the only way to really know is to try it yourself.
Anyone have plans for something like this that they would like to share? I’d love some project ideas.
If you want to play with FPGA, get instead a Lattice ice40 board:
I'm a noob here. Does it means it has ECC or does it support ECC?
"OTG" is such a gallingly stupid, uninformative term.
Do you expect your Keyboard to act as a USB Host?
If your Keyboard were USB OTG, then it would be a keyboard when plugged into a computer, but a mouse could plug into the keyboard and then the keyboard would be the USB Host. This bi-directional feature would be useful for maybe a modern Commodore 64 like device or something (I dunno, just making stuff up).
Traditionally, USB OTG was for phones. They want to be a device when plugged into a computer, but the phones also want to accept a mouse/keyboard/USB Mass Storage.
"OTG" is inherently meaningless. Kind of like a "red flag warning" (for any CA readers).
On-The-Go: An OTG product is a portable device that uses a single Micro-AB receptacle (and no other USB receptacles) to operate at times as a USB Targeted Host and at times as a USB peripheral. OTG devices shall always operate as a standard peripheral when connected to a standard USB host.
You can get the rest of the details from the specification itself: https://www.usb.org/document-library/go-and-embedded-host-su...As to "meaningless is fine..." no. And doubly no to the abbreviation of a meaningless name.
"Dual-mode" or "dual-role" USB would make at least some sense and convey some information.
a) A keyboard has a little computer in it too. Fundamentally they're both computers. It's not the "computerness" that matters, it's "is this normally a peripheral?"
b) This is normally a peripheral - you connect it to a host computer to program it.
You underestimate the complexity of modern protocols and the amount of computational power in everyday devices.
All USB devices have more compute power than the entirety of the Apollo Moon Lander program. And we use that compute power to format USB checksums, USB packets, and other such protocol details.
In practice, a keyboard today has the compute potential exceeding that of supercomputers of decades past. We just don't think about it very much.
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A modern mouse is more obvious, in that it uses convolution kernels over the scanned 2d infrared picture to figure out if the image moved right, left, up or down about 100x per second and reports the results to the host.
That's how optical mouse works. Lots and lots of matrix multiplications and 2d digital signal processing...
1. You can plug them into your PC and they act as a device (e.g. mass storage device for downloading your photos, drawing power to charge)
2. You can plug devices into them, and they'll act as a host (e.g. you can plug in a mouse if your touchscreen is broken, download the photos from your non-smartphone camera onto your smartphone, supply power to charge something else)
3. They'll do all this through a single port.
Hardly any normal people use these capabilities, as the cables are somewhat rare and the software support is somewhat patchy. But if you're buying a development board ready to make your own product, you can read this as "can be a usb host or device, whichever your product needs"