I don't know if I'd go quite that far, but the 6502 definitely had some RISC-ish features.

The Page 0 addressing mode basically let you use the first page of RAM more or less as 256 extra 8-bit registers (or 128 16-bit registers, etc.), as those locations could be accessed faster and with fewer instruction bytes than locations elsewhere in RAM.

A fair number of languages were implemented on 6502-based machines by using multiple Page 0 locations to simulate wider registers.