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Comment by amelius | Hacker News Reader

Do any methods exist that utilize deep learning to drive the optimization?

Yes, see DREAMPlace -- "DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement".[1] The technique in particular rather reformulates VLSI placement in terms of a non-linear optimization problem. Which is how ML frameworks (broadly) work, optimizing approximations to high-dimensional non-linear functions. So it's not like, shoving the netlist it into an LLM or an existing network or anything.

Note that DREAMPlace is a global placer; it also comes with a detail placer but global placement is what it is targeted at. I don't know of an appropriate research analogue for the routing phase of the problem that follows placing, but maybe someone else does.

[1] https://github.com/limbo018/DREAMPlace

I also want to note that some people are looking at using ML/DL to generate placement solutions, even though DREAMPlace is still a key recent work in this area that at the core uses analytical placement, although cleverly using deep learning libraries and features.

For example, the VTR people are looking at RL to pick what actions to take during FPGA placement for their simulated annealing placer (see: https://ieeexplore.ieee.org/document/9415585).

I also know this paper/poster was indexed recently under OpenRevew but I'm still waiting for some more implementation details to look at: https://openreview.net/forum?id=6GR8KqWCWf

FPGA routing I don't think anyone has touched on using ML/DL but I do know that there is some talk about using ML/DL models with current routing approaches to replace search heuristics (think like replacing or augmenting something like A*) or do routability predictions. Certainly, there are probably many ways to use RL in routing as there are many places in current algorithms to intelligently make certain heuristic decisions.

Edit: I also want to note that there are a ton of works that also use ML/DL to tune the "hyperparameters" of EDA tools such as placers and routers. Think ML/DL for back-box non-linear optimization.

> The technique in particular rather reformulates VLSI placement in terms of a non-linear optimization problem. Which is how ML frameworks (broadly) work, optimizing approximations to high-dimensional non-linear functions. So it's not like, shoving the netlist it into an LLM or an existing network or anything.

Do you mean it uses gradient descent to find the optimum?

You can’t really do that for nonlinear functions

Well everybody in DL is doing it, and neural networks are nonlinear functions.

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