Comment by masfuerte | Hacker News Reader

Comment by masfuerte | Hacker News Reader

Parent Full thread

The BBC Master had an even funkier mode. The RAM bank accessed could depend on the current program counter.

Imagine a video display taking 16K of RAM. This would be situated between addresses 0x4000 and 0x8000. This same memory range also included non-video RAM. The hardware transparently selected the video or non-video RAM depending on which code was accessing it.

Specifically, if the program counter was at 0xC000 or above (i.e. code in the OS ROM was running) then accesses to the video range would go to the video RAM. But if the program counter was elsewhere (i.e. running user code or an application ROM) then accesses to the video range would go to user RAM, not video RAM.

Additionally, there was a hardware register controlling this so that user code could choose to directly access the video RAM, and OS code could access the user RAM.

There were also 8-bit home computers (like the Amstrad CPC and C64) where a different memory bank would be accessed depending on whether the CPU would do a read or write access, e.g. a read would access a ROM bank, but a write would access a RAM bank at the same address (usually called 'shadow ROM').

Huh? How do you read from the ram after you write to it?

You bank switch then. A common use would be to e.g. be able to use the ROM to load code into the RAM under the ROM and then bank switch, but also e.g. for extensions where you might want to first copy the ROM into the underlying ROM, and then patch whatever changes you wanted into before bank switching.

And sometimes you also don't need to read the written data back (for instance when writing to video memory).

I've been looking for a detailed explanation on this, because I would like to know how they read the PC.

The New Advanced User's Manual describes the flag at &FE34 on the Master and B+ and I've read this thing about using the PC from a few places but I haven't found any specifics.

Could you clarify? How do you know from the outside what's in the PC?

Would they not just mooch the address off the address bus?

Yep. The 65C02 has a SYNC output that goes high to indicate an instruction is being fetched on the current cycle. Since there is no cache, it's pretty simple to use this to determine the PC.

Thought so. From there, it is a bit of logic to map the chip selects to make the writes and reads come and go from the intended resources.

That's it then. I was missing the sync pin. Thank you.

Reply on news.ycombinator.com