Hacker News Reader

The default DDR5 ECC is not exposed to the outside, not reported to the OS.

You only caught errors on DDR5 because it's stability is very brittle. Market forces push it to the limit - everybody cares about the MT/s and runs XMP unlike previous generations.

View on HN

DDR5 seems to have optimistic XMP settings, whereas DDR3/4 were more conservative.

I have, however, had very good luck so far just buying faster DDR5 and then running it a little slower at the same timings, which is how I arrived at the idea that DDR5 XMP is usually too fast to be actually stable.

I think it's just the memory controllers not being as mature yet.

For some point of comparison: Intel 12~14th gen operate DDR5 at 4GHz with 2DPC (DIMMS per channel), AMD Ryzen 7xxx at 3.6GHz with 2DPC.

With 1DPC the numbers are slightly better, with Intel 12th at 4.8GHZ and 13th/14th at 5.6GHz and AMD Ryzen 7xxx at 5.2GHz.

All a far cry from the ridiculous overclocks at 6GHz and above.

XMP profiles are still seemingly more conservative for DDR4, since I would typically run my 3200MHz DDR4 at 3840MHz. That stopped once I added a couple mismatching sticks though, now I have to run the set at 3105MHz or the system won't POST. Not a particularly big deal.

Reply on news.ycombinator.com