This is really old news and sadly there wasn't anything new in this article, the issue remains. IBM [used to?] use eDRAM for their last-level caches which is a classic latency/capacity trade-off that seems reasonable.
There are some amusing typos, like "single-core"/"dual-core" where they meant port rather than core.
I’ve seen this topic make the trek from Stratchery to SemiAnalysis and now to SemiEngineering in the past month and a half. That’s how you know it’s a real one.