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Comment by automatic6131 | Hacker News Reader

Once again, the "process size" are marketing numbers. There's no actual feature measuring 1nm.

The actual transistors are around 40nm across [1]. They change the geometry of the features, either the shape of the transistor gate or even the method of power delivery. All really incredible features and worthy of awe. Just not actually making transistors with finger-countable number of atoms.

[1] https://www.wikiwand.com/en/2_nm_process

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I have often heard that these are “just marketing.” But humor me - where does the “1nm” even come from? What is the calculation that ends up spitting out 1nm, even if its invalid?

Basically, the calculation is: "previous process name x 0.6, rounded up", or something like that.

So you get 65, 40, 28, 20, 14, 10, 7, 5, 3, 2, 1 ...

The actual pattern was intended to follow "previous / sqrt(2)", such that every node would double areal density, and every two nodes would double linear density.

That should be x0.7 or /1.4 since it's sqrt(2).

literally it is made up

No, it's sort of a "transistor density equivalent"

Right, so made up.

No, it's computed based on transistor density

"Pentium Rating" of x486 (so called x586) uPs

It used to be that it was a linear scaling factor. So if you moved from, say, 40nm to 20nm, you'd see a 4x increase in transistor density. In the early days of VLIW scaling (roughly from 45nm and up), that really did work by just "making everything smaller". And in that world, the smallest thing was generally the size of the middle/active region of the transistor on top of which the gate sat, so the "gate length" (which is actually the *width* of a resist line that crosses the transistor) became the standard.

But then they started having to cheat: you can take a big transistor and "fold" it vertically to be smaller but still have the same gate area, etc... The actual feature sizes may not have changed much but you have the 2x density increase, so you name your new node "32nm" even though the actual width of the gate feature when seen from above didn't change, etc...

But then somewhere around 10nm everyone just gave up and started handing out random numbers. TSMC's 3nm process is not remotely a 2x density increase over 5nm, for example.

Sort of. Down to around 14nm nodes, maybe lower, the number was the actual minimum length of the transistor gate. Somewhere thereabouts the transistors weren't shrinking as much but they needed the number to go down so it became some rough estimate of PPA (power performance area) improvement - it's not just density.

There's also a distinction between "drawn length" which is the number specified by the designer, and the actual feature size on silicon. This can be scaled up or down either completely arbitrarily (meaning the drawn length is a total sham) or optically (meaning the drawn length is real but the chip is fabricated with a magnification <1)

Oh no, long before 14nm. A quick google tells me that the gate pitch on Intel 14nm is 70nm!

Obviously there's a ton of complexity here and lots of cheats and optimizations were done over the decades that weren't directly related to linear sizing. But I stand behind the threshold I gave: the big discontinuity in the industry, where "node size" and "feature size" clearly began to significantly diverge, was the introduction of finfet/tri-gate transistors in Intel 32nm.

Gate pitch is not the same as gate length. The smallest feature size is usually the transistor gate length. In Samsung 14nm processes for example the drawn fin length is in fact 14nm. The actual physical size of the fin is closer to 8nm but I believe the whole structure is still close to 14.

The "divergence" started happening long before finfets where Intel is concerned, but they weren't manufacturing for anyone else. For the rest of the foundries, it still followed somewhat logically, if not exactly, down to 14 at least.

> “ But then somewhere around 10nm everyone just gave up and started handing out random numbers.”

Hahaha

It's supposed to reflect transistor density. If you take a chip made on a say 90nm process and shrink it by 90x it should have approximately the same transistor density as a "marketing 1nm" chip. The scaling stopped around 45 nanometers.

You can see this if you compare 2 processes: Intel 45nm had 2,779,468 transistors/mm², and the Apple A14 (7nm) had a transistor density of 134,100,000 t/mm²

2,779,468*(45/7)²=114,865,769, so the two are quite close.

https://en.wikipedia.org/wiki/Transistor_count#Microprocesso...

The size used to correspond to minimum feature size. A transistor consists of multiple features and used to be fairly planar with things arranged side by side more or less.

As it became harder to shrink the minimum feature size, they figured out other ways to shrink. For example various ways of stacking things on top of each other rather than having them side by side[1].

As such they could cram more transistors in the same area compared to a planar transistor, and hence you got the same effect as shrinking the minumum feature size.

Not sure exactly how they name things, but one could calculate what feature size would have been required to get a given transistor density using a plain planar transistor, for comparison.

[1]: https://semiengineering.com/from-finfets-to-gate-all-around/

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