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Comment by bee_rider | Hacker News Reader

> Initially announced in February 2022 during Intel's Investor Meeting, Intel is splitting its server roadmap into solutions featuring only performance (P) and efficiency (E) cores. We already know that Sierra Forest's new chips feature a full E-core architecture designed for maximum efficiency in scale-out, cloud-native, and contained environments.

When they say splitting like that, do they mean there won’t be chips that feature both?

Xeons with homogeneous big cores and Xeons with homogeneous little cores… why not call it Knights Forest?

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For servers it makes no sense to have hybrid CPUs with heterogeneous cores.

Where needed, you can put in the same rack several servers with big cores and several servers with small cores, in a proportion appropriate for the desired application. When the big cores and the small cores are in different sockets and they do not share coolers, the big cores can achieve maximum speed without being slowed down by the heat produced by the many threads that might be run simultaneously on the small cores.

AMD already has both server CPUs with big cores (Genoa and Genoa-X) and server CPUs with small cores (Bergamo and Siena). AMD's strategy seems wiser, because their small cores are logically equivalent with the big cores, but they have a smaller size and a better energy efficiency due to a different physical design.

Intel's strategy of implementing distinct instruction sets in the big cores and in the small cores is an annoying PITA for software developers.

The main uses I’ve seen for extra, light cores are redundancy against hardware failures, physical isolation, and I/O coprocessors. (Other than strictly using them for low-power operation that is.)

For redundancy like NonStop pairs or secure decomposition, the IPC must be really fast so they can work in lockstep or pipelines.

For I/O processors, the efficient one can handle interrupt processing while the performance core focuses on main application. Like in a mainframe with the hardware more condensed.

A separate socket per logical domain with its IPC overhead might not be as cost-efficient as heterogenous CPU’s. That’s also before I consider putting the new chips in existing, low-cost servers with all servers having the same chips. That might have cost and management benefits on top of it.

Knights featured AVX512F and were best at heavily SIMD workloads. Sierra Forrest is bad at these jobs of workloads, lacking AVX512 and having only 16 byte execution units, so their AVX(2) throughput is also poor.

They're thus going after a very different market.

The Xeon Phi reference that I was looking for - this is basically Larrabee all over again, now CPU only.

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