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In FPGAs you are literally programming the enablement of individual logic gates. That's it.

There is no DMA or command ring, you have to implement it yourself.

The FPGA bit code itself is extremely propertiary to each vendor as the nature of controlling all the logic sauces is all secret sauce. So you have to use the vendors tooling.

If we have to go thru a closed source or brain damaged hardware programming interface, this is a loss for us.

It has basically always been this way. Xilinx wasn't different before this announcement. Altera wasn't and isn't either. Some of the smaller lattice designs are a bit more open, but are a different market segment.

You will use Vivado and you will like it!

An FPGA is a blank slate, more so than a CPU is, the programming interface is whatever the user wants to implement (including ring buffers and DMA or whatever).

> I wonder what is the hardware programming interface.

Vivado

> Then quickly getting up and running a shmol RV64 core... and I guess this is hacker paradise.

https://github.com/SpinalHDL/NaxRiscv