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Exactly, this is what Apple are doing with their “Ultra” architecture.

It really is the way forward.

The chiplet design is another innovation like FinFET and even EUV that is allowing for more transistors closer together. The interconnect for instance on the blackwell means no timing issues.

The transistor size is already closing in on 1nm, there will be innovation there eventually, but any step can be a stepping stone. I don’t see the issue here.

Transistors are nowhere close to 1nm right now. Current 3nm stuff is something like 20-40nm wide depending on how you measure it.

You are talking for Servers right? Else how do you plan to cool such a beast?

Won’t it have large surface area too?

Chiplets will be underclocked to run close to their most efficient power / performance frequency.