Construction of n-dimensional Morton codes of an arbitrary bit length is regular enough that you can generate optimal shift/mask sequences at compile-time. There are also simpler generator algorithms that are slightly less optimal (e.g. in a few cases there may be an unnecessary shift/mask step).

Intel microarchitectures added fast ALU instructions (PDEP/PEXT) that can directly effect this as long ago as Haswell (2013) but AMD only very recently added comparable instruction implementations so portability of these instructions is an issue. Also, depending on the dimensionality and bit length of the code, there may be a few cases where the optimal shift/mask version will be about as fast without the portability concerns.