Qualcomm's Oryon LLVM Patches

I think they should probably set LoopMicroOpBufferSize to a non-zero value even if its not microarchitecturally accurate. This value is used in LLVM to control whether partial and runtime loop unrolling are enabled (actually only for that). Although some targets override this default behaviour, AArch64 only overrides it to enable partial and runtime unrolling for in-order models. I've left a review comment https://github.com/llvm/llvm-project/pull/91022/files#r16026... and as I note there, the setting seems to have become very divorced from microarchitectural reality if you look at how and why different scheduling models set it in-tree (e.g. all the Neoverse cores, set it to 16 with a comment they just copied it from the A57).

Interestingly Oryon is at least 2 years late if not 3. And we are seeing the exact same problem with previous Qualcomm attempt in Custom core, it is that ARM has caught up. Cortex X4 is not far off M2, and Cortex X5, which we should have more details later this year is expected, according to their CEO to have the largest IPC improvement in recent Cortex X history. If any Qualcomm competitor could simply buy a similar performance design at a lower cost, what competitive advantage does Qualcomm's custom core have?

And from what we are seeing, even the M4 design isn't all that far off from M2 either. Apart from the support ARMv9 which makes certain test in GB6 much quicker. It would be interesting to compare Oryon, M4 and X5 next year. Or we have simply arrived at another point where IPC improvement reaches a plateau.

Current leaked or early information of Cortex X5 from Mediatek suggest 1610 GB6 Score at half the clock speed of M4. Assuming no memory bottleneck it would have 3220 GB6 compared to 3800 GB6 of M4. Both on ARMv9.

  sadly the size of the L1D is not said in this patch

This is because SchedMachineModel doesn't have an entry for cache sizes. However, if you have an actual CPU to run benchmarks on, it's pretty straightforward to empirically determine cache sizes with lscpu -C. This should list L1D, L1I, L2 and L3 cache sizes.

1. Still ARMv8.

2. "*Nuvia Inc* Oryon processors"

This seems shocking. How long before Apple sues Nuvia?