> This scheme appeared with Tremont, where it could only switch decoders at taken branch boundarie and Gracemont improves load balancing between the two decode clusters by automatically switching, instead of relying on taken branches. That helps performance in very long unrolled loops, which could get stuck on one decode cluster on Tremont. When we tested with longer loop lengths, we didn’t see any drop off in Gracemont’s instruction throughput:
- https://chipsandcheese.com/2021/12/21/gracemont-revenge-of-t...
Also back in those days 32bit x86 with it's anemic 8 GP registers (and stack-based-fpu) it was hard to avoid any dependencies w/o trying to calculate memory positions, nowadays we have 64bit x86 with 16 GP registers and separated FPU XMM registers (compilers can leave much more in memory and registers are probably far easier to do dependency resolution on).
Oh and a theory could be that JS,Java,C#,Rust,etc code with lots of non-taken safety barriers(out of bounds, type-tests,etc) has probably been analyzed and been found to be a prime candidate for parallell issue.