I'd love to hear more about the low power design. You mentioned going for a MSP430 on here, and the high level architecture blogpost has some infos about the power domains too. But I'd love to see another blog post with some more nitty-gritty powersaving stuff.
I was also wondering... have you thought about adding a simple streaming compression algorithm to increase battery life? Less data to write would mean less time of VDD_B being active. Could maybe even be implemented on the FPGA. I was thinking of something like delta encoding, with two different code lengths for small and big brightness changes (per color channel.
E.g. first bit 0 -> 5 bits of +/-32 brightness delta following. First bit 1, 11 bits of brightness delta.
You'd loose some minimal information if brightness changes by more than 2048 between two pixels, but you could just "smear" that change over two consecutive values (e.g. [0, 0, 4096, 4096, 4096] would end up as [0, 0, 2048, 4096, 4096])