Amazing that it's apparently implemented in plain Verilog, not SystemVerilog; or did I miss something? Would be interesting to hear from the author what the motivation was for this choice.
At a guess it's because the author has been using Yosys for some formal verification work and maybe for doing some synthesis trials and it doesn't support system verilog natively. Though things are improving there: https://github.com/chipsalliance/synlig
But if they do formal verification, then at least SV assertions should be present; will talke another look at the code.
Yosys supports very basic SVA (immediate assert/assume, $past etc) in addition to Verilog 2005