SiFive announces high performance RISC-V cores for Datacentres | Hacker News Reader

SiFive announces high performance RISC-V cores for Datacentres

sifive.com

26 pointsfork-bomber13 comments

SiFive also updated the website, and gave the first SPECint2017 score: Their P870-D is supposed to have a >2 SPECint2017/GHz.

https://www.sifive.com/cores/performance-p870d

Wouldn't that make it a monster?

What RISC-V needs to take off, IMO, is laptop/workstation solutions. I believe what has given ARM a huge leg up in terms of development mindpower is Apple's M1. Ideally for RISC-V, there'd be an apple product with it inside. Barring that, you are basically asking for new software for RISC-V to be developed on non-risc-v devices. That can work, but I think it really slows down adoption.

There are a few, but there hasn't really been high enough performance SoCs/cores to make them worthwhile. Framework has a RISC-V based motherboard in the works, but it has less compute power than a Raspberry Pi 4 (JH7110) so it's of marginal use as an everyday machine. I think it will just take time, a lot of time, for RISC-V to get to the same spot that ARM is in now, but I am optimistic that it will get there.

This is what I had hoped horse creek/horse canyone was going to be before it was killed off. The board also needs a stable/updating linux distro like raspberry pi os is along with VS Code and language server support.

The spacemiT K1/M1 SoC is the best that you can get now. The CPUs implement RVA22+V, which is the newest spec available in hardware.

There is:

- Banana Pi BPi-F3[0][1], a SBC.

- Milk-V Jupiter[2][3], a mini-ITX board.

- DC Roma II [4][5], a laptop.

Performance-wise, each core in this SoC is between that of Rpi 3b+ and Rpi 4, and there's 8 of them.

By 2025Q1, Milk-V Oasis[6] is expected, with 16x SiFive P670 (Zen1-tier IPC) and 8x X280.

Late 2025, it should be possible to buy something with P870 (the next gen).

RISC-V is catching up with the top performers very quickly.

0. https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3

1. https://www.youtube.com/watch?v=GZGryhBnkV0

2. https://milkv.io/jupiter

3. https://youtu.be/YxtFctEsHy0

4. https://deepcomputing.io/product/dc-roma-risc-v-laptop-ii/

5. https://youtu.be/3mhd98AGNXQ

6. https://community.milkv.io/t/introducing-the-milk-v-oasis-wi...

Multiple companies have Apple M1 level RISC-V cores designed and announced and ready for chip makers to license, including Akeana which came out of stealth mode a couple of days ago.

It only remains for someone to design these cores into an SoC, manufacture it, and get it onto boards and into the market, a process that typically in the past has taken around 3-4 years but may be accelerating. Keep an eye out around 2026-2027.

Meanwhile, we'll have early Core i3/i5/i7 level performance in RISC-V SBCs by this time next year (the manufacturer is saying Q1, but I don't quite believe that), but with a lot more cores. That's leapfrogging over Pi 5, Rock 5, Orange Pi 5, which is already a pretty usable machine.

Very excited for this but would really appreciate more details. Core frequency, SRAM volumes, CXL generation, PCIE lanes, memory channels... or even ballpark performance estimates.

Has anyone here played with their embedded chips? What was the experience?

This appears to be a press release about core designs (AMBA is an on chip interoperability standard, by Arm), whereas you are asking primarily about SoC features.

Yes, the press release is empty of any content that could be used for a comparison with alternative solutions. Nothing about core area, power consumption per core or any performance metric.

The product page[0] has some information, and a link to an article[1] on the hot chips 2023 presentation.

0. https://www.sifive.com/cores/performance-p870d

1. https://chipsandcheese.com/2023/09/03/hot-chips-2023-sifives...

There wasn't much discussion in the last thread, but Akeana announces their RISC-V portfolio yesterday: https://news.ycombinator.com/item?id=41239474

Among others, it also includes a very high performance core.

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