It's just the X280 and some of the open-source long vector designs that have 1-cycle-per-element vrgather AFAIK. They X280 is more of an accelerator than actual end user core. All other application class cores I know of have a "fast" LMUL=1 vrgather.

The linked discussion was about LMUL>1, which doesn't matter because you can unroll it into multiple LMUL=1 vrgathers if you don't cross lanes. That even uses fewer vector registers. LMUL>1 vrgather should imo only be used if you need to actually cross vector register lanes.

I think a fast 128-bit lane shuffle is certainly unnegotiable for application class processors, but I'm not sure a dedicated instruction is needed for them, because for them a fast LMUL=1 vrgather is similarly important. You won't see many processors with larger then 512 VLEN running regular software from the binary ecosystem and if they do, they'd better execute a LMUL=1 shuffle quickly, especially if it's within 128/256/512-bit lanes, whatever your internal execution unit width is.