MultiQueue-Based FPGA Routing: Relaxed A* Priority Ordering-Improved Parallelism [pdf]
eecg.utoronto.ca
eecg.utoronto.ca
I'm also wondering how congested these input designs are - I don't know much about the benchmarks used. Extremely congested designs can take a much, much longer time to route so an improvement there either in runtime or QoR could be useful.