Ask HN: Are there open source flow graph based Verilog generators?

I've decided to take a stab at an open source tool for HDL generation called flow - https://github.com/spetca/flow-hdl/tree/main. It's like simulink and gnu radio for building hardware via a flowgraph. It's completely in the browser/client side. You cannot simulate or do anything complex (yet) so comparing it to simulink and gnu radio is a bit of a stretch at the moment.

I'm wondering if HN knows if something like this already exists before I invest in this rabbit hole.