Most importantly, it's been just a few years since we could start getting reasonable RISC-V boards.
“As of June 2019, version 2.2 of the user-space ISA[46] and version 1.11 of the privileged ISA[3] are frozen, permitting software and hardware development to proceed. The user-space ISA, now renamed the Unprivileged ISA, was updated, ratified and frozen as version 20191213”
So, it’s more like 5 years old, compared to ≈40 for 32-bit x86, ≈20 for 64-bit x86.
P550 was announced shortly after these specs were ratified, so it's one of the earliest RVA22 designs.
I am expecting there'll be others we will get to see this year.
ISA design is a complex endeavor. Arch64 benefited from multiple factors directly attributable to ARMs prior art, domain knowledge, and market positioning.
There is a huge distinction between a globally recognized and dominant ISA engineering firm coming out with a “new” ISA that their engineers had been prepping for for years, and the effort required to create a novel ISA and ecosystem from scratch.
One is just another day at the office, while the other is a very riscy endeavor that requires amassing the talent, creating incentives, creating an engineering culture, and trying to create a niche in a market that was arguably fully populated by other options. And then, you still have to create an entire family of ISAs to match various specification levels.
It’s not an apples to apples comparison.
(which you didn’t explicitly state, so I apologize for thinking it that way)
….of the launching of arch64 with the launching of the RiscV ISA.
They were both theoretically clean slate designs, but one was made by a bunch of academics and the other by a company with decades of ISA design expertise. I’d expect the latter to be much, much more mature, all other things being equal.
At any rate, what riscV really did so far was to make 8bit MCUs irrelevant. I used to use a lot of 8 bit parts even with M0 around, but now with chips like the CH32v003 and family, it’s just ridiculous to even contemplate.
I mean you can hook up an 8pin MCU and a couple of resistors to a vga monitor and a keyboard and have a a computer in a heat shrink tube that walks circles around my ancient apple II for $0.60.
And if you want WiFi, BLE, and some other wireless stuff, with 3x the speed and 100x the memory, the riscV esp32 chips come in at about $1, and they can do pretty strong edge AI. It’s all just silly at this point, and it’s riscV that caused that sea change.
FWIW I agree that AArch64's launch was not the same as the RISC-V launch. There has clearly been a lot more work required to boot the RISC-V ecosystem and they have made amazing progress. Arm had the advantage of incumbency and a lot more resources.
At the same time I think the have oversold progress on application level processors and I don't think this does RISC-V any favours at all. Arm has a lot of experience and the general tone from some of the RISC-V commentary is that they got it 'wrong' with AArch64 which, to be charitable, is unproven.
If you look at an arch like x86 or ARM it was designed right before chips were released, and then extended over time. The same goes for the X protocol, it simply extended previous versions.
If you are designing something from the ground up to avoid the inherent problems of an existing system, it is reasonable to take time and research design problems to make sure you don't recreate the same issues (which would defeat the point of the redesign). It doesn't compete on the same time-frame as an extension of an existing system.
September 2019 for the base specs being ratified.
But even that isn't the true starting gun for anything but basic MCU.. For high performance, it's RVA22. The relevant specs were only ratified in December 2021.
It takes 3 years from IP to chips, and thus we are seeing the first RVA22 chips now.
No surprises there.
Is this 7 nm node really older than raspberry pi 5's 16 nm node?
> Next up is TSMC’s 12 nm FFC manufacturing technology, which is an optimized version of the company’s CLN16FFC that is set to use 6T libraries (as opposed to 7.5T and 9T libraries) providing a 20% area reduction. Despite noticeably higher transistor density, the CLN12FFC is expected to also offer a 10% frequency improvement at the same power and complexity or a 25% power reduction at the same clock rate and complexity.
They optimised for density and power, not frequency. A lot of the benefit they're claiming comes just from this.
https://www.anandtech.com/show/11337/samsung-and-tsmc-roadma...