JLC never added the pour for me. Not even for larger boards. Not sure this is up to date.

In any case, if you have to add the top layer pour, make sure to:

1. Use high clearence so as not to introduce edge coupling that changes your carefully calculated trace impedance.

2. Stitch the pour to actual GND with vias. Thoroughly. Do not let it float.

You do calculate trace impedance, right? :-)

I am only half joking. Some components let you specify source impedance. RP2040 has GPIO drive strength in mA, but they roughly correspond to 12 mA / 33 Ohm, 8mA / 50 Ohm, 4 mA / 70 Ohm and 2 mA / 100 Ohm. I usually use 100 for 2 layer boards and 70 for 4 layer boards. This is effectively series termination.