Can anyone explain what might be going on here, especially as it relates to power consumption? I thought (bigger die ^ bigger wires -> more current -> higher consumption).
For tasks that tend to scale well with increased die area, which is often the case for GPUs as they're already focused on massively parallel tasks so laying down more parallel units is a realistic option, running a larger die at lower clocks is often notably more efficient in terms of performance per unit power.
For GPUs generally that's just part of the pricing and cost balance, a larger lower clocked die would be more efficient, but would that really sell for as much as the same die clocked even higher to get peak results?
I should've considered this, I have an RTX A5000. It's a gigantic GA102 die (3090, 3080) that's underclocked to 230W, putting it at roughly 3070 throughput. That's ~15% less performance than a 3090 for a ~35% power reduction. Absolutely nonlinear savings there. Though some of that may have to do with power savings using GDDR6 over GDDR6X.
(I should mention that relative performance estimates are all over the place, by some metrics the A5000 is ~3070, by others it's ~3080.)
Old source, but this says the power cost of increasing the clock frequency is cubic: https://physics.stackexchange.com/questions/34766/how-does-p...
Anyway, expecting good earnings throughout the year as they use Battlemage sales to hide the larger concerns about standing up their foundry (great earnings for the initial 12gb cards, and so on for the inevitable 16/24gb cards).
They might be targeting a lower power density per squad mm than compared to amd or nvidia, focusing more on lower power levels.
Instruction set architecture and layout of the chips and PCB also factor into this as well.
I am not a semi expert but bigger die doesn't mean bigger wires if you are referring to cross-section, the wires would be thinner meaning less current. Power is consumed pushing and pulling electrons from the transistor gates which are all of the FET type, field effect transistor. The gate is a capacitor that needs to be charged to open the gate to allow current to flow through the transistor. discharging the gate closes it. That current draw then gets multiplied by a few billion gates so you can see where the load comes from.
All things being equal, a bigger die would result in more power consumption, but the factor you're not considering is the voltage/frequency curve. As you increase the frequency, you also need to up the voltage. However, as you increase voltage, there's diminishing returns to how much you can increase the frequency, so you end up massively increasing power consumption to get minor performance gains.
If Intel is getting similar performance from more transistors that could be caused by extra control logic from a 16-wide core instead of 32.
This strikes me as not a particularly useful metric, or at least one only indirectly related to the stuff that actually matters.
Performance/watt and performance/cost are the only metrics that really matter both to consumer and producer - performance/die size is only used as a metric because die size generally correlates to both of those. But comparing it between different manufacturers and different fabs strikes me as a mistake (although maybe it's just necessary because identifying actual manufacturing costs isn't possible?).