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Comment by throwaway_3133 | Hacker News Reader

This is what happens when you advertise a shuttle run for "open source" designs, brazenly backdoor everybody's chips with a Management Engine (google "eFabless Caravel") and then, to top it all off, act like you can just show up at CCC and pretend everything is fine:

https://media.ccc.de/v/38c3-the-design-decisions-behind-the-...

Video from 38c3 talk 2024-Dec-29; question at time 31min:17sec.

This company, and its enablers (formerly) at Google, set back the progress of open source chip design by at least three full years with this bait-and-switch insanity. The people who could see through the ruse wouldn't touch it with a ten foot pole; meanwhile it sucked up all the students, momentum, and funding.

Think about what three years of progress is worth in the tech industry.

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It's not a backdoor.

Caravel is fully open source. You can audit it. There is no ROM (except for a project ID), just 1.5KB of RAM, a CPU, a few peripherals and (most importantly) the pad ring.

Caravel is a (questionable) attempt to lower the barriers of entry to silicon design, both the cost and required skill.

It lowers cost, because every single chip on the MPW is the same size, and can be tested with a common interface. They can test the RISC-V core and pad ring to get a good indication of the die quality (theoretically they can upload user-submitted code to test the actual design, but I don't think have implemented that), and only package up the highest quality dies that are most likely to work.

It lowers required skill, because the user doesn't have to worry about getting the pad ring right. When they receive their chip, they are guaranteed to have a working RISC-V core, and caravel provides a bunch of logic analyser probes you can hook directly into your design to debug why it's not working.

It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate.

The Caravel harness makes it very clear what the target market for the eFabless product is. It's not for end products, you only get a few chips. It's for people, especially hobbyists to learn how to do silicon design. (Though, IMO it's nowhere near cheap enough for that target market.)

If you want an actual end product, you should be contracting either with eFabless or directly with Skywater for a full wafer with a custom pad ring.

> It also meant anyone who actually wanted a CPU core in their design got something that was guaranteed to work and easy to integrate.

in theory only.

caravel had hold time violations and the pin configuration mostly didn’t work for the first 5 or 6 sponsored OpenMPW shuttles.

Yeah... guaranteed after the teething issues.

My understanding is that there were problems with the whole Open PDK, and that most designs would have run into similar issues even if Caravel wasn't preventing IO configuration.

The didn't ship those early OpenMPW runs out at all, the designs where resubmitting to later runs. In a way, the incident proves the point: Caravel allowed them to quickly prove their yield for those early shuttles was essentially 0%, without needing to test the user design.

How would you do a multi-project chip without something like a "management engine"? By the nature of semiconductor fabrication, you have a bunch of identical chips, but you want each contributor to the chip to be able to use it for testing their own contribution. It seems like that means you need some way to dynamically configure which of the many projects on the chip are actually connected to its I/O pins?

To clarify, since unfortunately griefers are flagging your comment to impede the discussion, so I'm not allowed to reply to it: Tiny Tapeout is a multi-project chip, not a multi-project wafer (though it is one chip in a multi-project wafer). Typical minimum die sizes are 0.8mm², which is about 2 million potential transistors in 130nm processes. That's big enough to put many projects on a chip. That's why Tiny Tapeout cost US$300 while MPW prices start at about US$3000 and more typically US$9999+.

It's a multi-project wafer not a multi-project chip.

They cut the wafer apart into individual chips. There is one project on each chip.

This has been going on since the 1970s. It is a very well-understood process.

All eFabless designs for the first two years of the program were multi-project wafers with single-project chips. And they still required the management engine.

Over the past year they tried an experimental "multi-project chip" (first samples shipped 14 months ago). But the management engine was a requirement long before this happened.

GP seems to have edited their comment, but I can't edit mine (even though it is only 8 minutes old)

Tiny Tapeout is a multi-project chip not a multi-project wafer.

Sidenote: On HN you can often get downvoted/flagged not only for what you say, but for the way you say it. I wouldn't really call it griefing, rather a call for more civil discussion. If an account is new or a throwaway it gets held to this standard even stronger because no one really wants to see a HN that's flooded by throwaway accounts writing Reddit style comments.

The comment in question said, "It's a multi-project wafer not a multi-project chip. They cut the wafer apart into individual chips. There is one project on each chip. This has been going on since the 1970s. It is a very well-understood process." There is absolutely nothing uncivil about that comment, and it clarified that we were talking about slightly different things, thus leading to a resolution of the apparent disagreement and, I think, broader perspective for both of us.

The only even slightly uncivil thing about it would be the implication that I didn't know what MPW was, but in fact that was entirely plausible and would have been an important lacuna to correct were it true.

It was an exemplary comment, and the people who flagged it so that I could not reply were being a pain in the ass for no reason.

Why do you need a management engine for that? Couldn’t you just bond the connections to the ones you want and leave the other disconnected? Basically just have all chips next to each other on the die and only use one?

I/O pads (and their drivers) take up a huge amount of space. For some simpler ICs their die size is determined by their Pads.

Yes, Tiny Tapeout has its own MUXing layer to select which user project should be connected.

The Caravel management engine is used for single project chips, but it is innocuous. It just allows debugging and probing signals, and use of common I/O structure for different user projects. You don't have to actively use it.

It's hardly hidden, too: you have to instantiate it.

That was a front door not a back door! They were 100% open about the fact that it was there and most people wanted it to be there. If it didn't exist they would have to invent it. Why should I be the slightest bit upset about this?

You shouldn't. It's an entirely sensible thing for them to have done. Integrating IO and test is a massive time sink, it's a chore. People don't spend much time on it and it easily goes wrong and the whole thing is toast. Mandating the use of a fixed block to solve all this, at the sacrifice of some flexibility is what the majority would want. I've been doing this 15 years, I have experience of taping out real-life products that need to work. I can only assume the person complaining has different experience.

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