Zero ASIC launches first open standard eFPGA /w open-source bitstream, toolchain | Hacker News Reader

Zero ASIC launches first open standard eFPGA /w open-source bitstream, toolchain

zeroasic.com

36 pointstranspute5 comments

At a quick glance, couldn’t find any information about their LUT/slice/whatever they call their primitive.

1) Is it flash or ram based? Flash based LUTs are still a huge differentiator for Microsemi in aerospace due to SEU immunity, and they pay lip service to aerospace.

2) Assuming it’s RAM based, what access to that RAM do they provide? Do they allow using LUT (clusters) as micro-RAMs like Xilinx etc do? Port count?

3) 4-LUT vs 5-LUT vs 6-LUT? Two output support? Carry chains? Flexibility of carry chains? Flip-flops per LUT? Latch support for flip-flops?

Looks like they're claiming everything under the sun for 3). https://github.com/siliconcompiler/logiklib/blob/main/logikl... and https://www.zeroasic.com/fpga-architect say more. I'm very skeptical though. They claim binary compatibility? I don't know what that means for an FPGA. They seem to be testing all CLB vs some DSP/BRAM macros. What does it mean to have binary compatibility between those? Usually you don't want that. The design should be optimized for the device it's on. I don't want to take an fmax hit because someone may be using a soft multiply or something like that. Only time will tell.

The only novelty claimed here is transparency. Binary compatibility is possible by documenting the complete architecture and the sequence of bit stream loading. It only refers to devices in the same architecture (eg z1000).

We'll see whether binary compatibility is a big deal to folks. Some would argue that you can always recompile the source code. There are applications where that is not an option...

Eh, it’s a 4-LUT. If 4-LUTs were good enough, I’d stick with Microsemi. As it is, their only advantage over 6-LUTs is that they’re much less awkward to be overhead discussing by someone who doesn’t know FPGAs. (“6-LUTs are great” can raise some eyebrows.) The ratio of routing to compute just doesn’t match the problems I have experience with, and the reaction to rebalance this tends to be to omit other features (second outputs, shift register mode, wider muxes) that really, really pay off.

First off, this is an eFPGA core not a chip. It's intended for folks who want to build their own ASICs with a small amount of embedded FPGA logic.

The LUT is a boring text book 4-LUT. Fancier versions are in the works. The point of the first standard is to be the lowest common denominator of FPGAs that anyone can implement, else the threshold is too high. Kind of like RV32I.

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