RISC architecture did change everything
wired.com
wired.com
I always took this to be about the overall system (culminating in graphics) performance, as Dade continues "It's not just the chip. It has a PCI bus". And in the previous scene the dudes started off talking about the video capabilities, modem, etc. It really was a magical time where there were constant new advances across every single subsystem and peripheral.
How else could you pronounce it?
The first three letters could be "Rice" or "Rise" instead of "Riss".
I suppose you could have a soft "C" - "risch" - but that's a stretch and reminds me of Sean Connery.
Never underestimate the power of people to put weird sounds to letters. I used to do a lot of network stuff and somebody once pronounced MPLS (which you very much need to spell out) as "mipples" and it scarred me for life.
What is obvious to you and I is not always obvious to everyone else
Quote: “The Power Mac G4 is so fast that it is classified as a supercomputer by the U.S. government, and we are prohibited from exporting it to over 50 nations worldwide.” - Steve Jobs
(e.g. 'RISC being the future' was already a popular meme in the late 80s - however competing with 'transputers being the future')
> Who[m] should we thank? he [Patterson] asked. (Given that WIRED’s parent company has a deal with OpenAI that lets ChatGPT mine our content, we should thank old WIRED stories, among others.)
I wish Calista Redmond all the best at RISC-V International.
And if anything over the past 30 years have shown CISC won performance computing. That is everything from PC, Smartphone or all the way to server.
We need RISC for embedded and stay embedded.
Right tools for the right job. We need to stop the constant ideological / fashion / hype fighting in tech space and more good old fashioned proper engineering.
> if anything over the past 30 years have shown CISC won performance computing. That is everything from PC, Smartphone or all the way to server.
That is simply untrue. Smartphones and tablets are fully (or 99.99%) running on RISC -- Arm64 is a far more pure RISC than the original Arm32 was. Apple is doing great with its RISC-based M1/2/3/4 Macs.
Amazon introduced the first low end Graviton instances (same cores as a Raspberry Pi 4, but with up to 16 cores) in November 2018 and by 2022 they were reported to make up 20% of AWS capacity. They are quite likely 40% by now. Something like 90% of the top 1000 AWS customers use at least some Graviton instances.
> We need RISC for embedded and stay embedded.
Who is "we"?
And .. waaaaay too late for that.
> Right tools for the right job. We need to stop the constant ideological / fashion / hype fighting in tech space and more good old fashioned proper engineering.
Absolutely.
Which is why many of the best and most famous engineers in the business are now at RISC-V companies.
I guess we have a very different definition of RISC.
Edit: Actually found the argument [1] back then. Time flies. These debate has been going on for years if not decades so I wont go and rehash everything. There was another long thread on Realworldtech as well where Linus said something similar. But I cant find it right now.
I follow the definition of people such as Dave Patterson (who invented the terms "RISC" and "CISC"), John Hennessey, and John Mashey.
Here is a 1995 reposting of something Mashey first posted in this much detail in I think 1991, with proto-versions going back to at least 1988:
https://yarchive.net/comp/risc_definition.html
This post is regarded in the CPU designer industry as pretty much definitive.
The rest of the world has to free ourselves from "Made in US" technology.
Mostly it doesn't depend that much on the exact instruction set. It is possible to make a bad one, but x86 actually managed by more luck than anything to avoid the worst mistakes -- unlike, say, VAX or 68020.
Arm64 and Riscv64 don't have any of the bad features that make performance hard, so if someone competent tries with either one then they'll succeed. Obviously Apple and Qualcomm in the Arm world, and there are something up to half a dozen well funded companies with good experienced engineers in the RISC-V world.
Compared to motorla 68k, let alone monsters like VAX or PDP-10, x86 is very RISC-y, and AMD64 and intel/amd performance optimization guides (and general evolution of the platform) only moved it further towards RISC-like operation, with focus on load-store approach and most common memory addressing modes essentially becoming a nice wrapper for load-store around the instruction that can be easily pipelined RISC-style.
In fact, one can find nice discussions on why the "beautiful CISCs" like VAX and m68k provided very bad to insane barriers to speedup (m68k decoding honestly looks harder, VAX is a horror movie).
A lot of standard performance optimizations when compiling for x86-64 are a lot like "treat it like a RISC with fast optional load/store op in most instructions, but still prefer registers".
The legacy stuff is baggage, but obsolete instructions only cost silicon area, something that is constantly getting more abundant as transistors keep getting smaller. The only real difficulty is variable length instructions.
The solution to that is predicting the length of the instructions. This means that there are fast instructions (easy to predict) and slow instructions. The compiler can now avoid emitting them. The price of "CISC" becomes ever more insignificant.
The prime example is probably VAX, whose super orthogonal ISA (another "full CISC" hallmark) could lead to single instruction consuming multiple TLB entries (6 argument, up to 18 indirections assuming the arguments don't cause another page fault due to crossing pages), and another instruction could become longer than memory page.
Compare x86 where modern approach is essentially "you get free LEA instruction fused with execution of the main instruction" to the point using LEA instead of certain arithmetic ones is basic optimization