You know, for small-ish C projects I found that the easiest way to handle "which .h files do the .c files depend on" question is to just say "on all of them".

    SOURCE_FILES := $(wildcard $(SRC_DIR)/*.c)
    HEADER_FILES := $(wildcard $(SRC_DIR)/*.h)

    OBJ_FILES := $(patsubst $(SRC_DIR)/%.c,$(BUILD_DIR)/%.o,$(SOURCE_FILES))

    .PHONY: build clean

    build: $(BUILD_DIR)/$(TARGET)

    clean:
        rm -rf $(BUILD_DIR)

    $(BUILD_DIR):
        mkdir $(BUILD_DIR)

    $(BUILD_DIR)/$(TARGET): $(OBJ_FILES) | $(BUILD_DIR)
        $(LINK.o) $^ $(LDLIBS) -o $@

    $(BUILD_DIR)/%.o: $(SRC_DIR)/%.c $(HEADER_FILES) | $(BUILD_DIR)
        $(COMPILE.c) $< -o $@

So when you don't fiddle with inter-file/shared interfaces, you get an incremental rebuild. When you do — you get a full rebuild. Not ideal, but mostly fine, in my experience.

P.S. I just love the way that Make names its built-in variables. The output is obviously $@, but can you quickly tell which of $^ and $< give you only the first of the inputs? What about $> and $∨, do you remember what they do?