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Comment by joha4270 | Hacker News Reader

So, a Systolic Array[1] spiced up with a pinch of control flow and a side of compiler cleverness? At least that's the impression I get from the servethehome article linked upthead. I wasn't able to find non-marketing better-than-sliced-bread technical details from 3 minutes of poking at your website.

[1]: https://en.wikipedia.org/wiki/Systolic_array

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I can see why systolic arrays come to mind, but this is different. While there are indeed many ALUs connected to each other in a systolic array and in a data-flow chip, data-flow is usually more flexible (at a cost of complexity) and the ALUs can be thought of as residing on some shared fabric.

Systolic arrays often (always?) have a predefined communication pattern and are often used in problems where data that passes through them is also retained in some shape or form.

For NextSilicon, the ALUs are reconfigured and rewired to express the application (or parts of) on the parallel data-flow acclerator.

Are the GreenArray chips also systolic arrays?

My understanding is no, if I understand what people mean by systolic arrays.

GreenArray processors are complete computers with their own memory and running their own software. The GA144 chip has 144 independently programmable computers with 64 words of memory each. You program each of them, including external I/O and routing between them, and then you run the chip as a cluster of computers.

[1] https://greenarraychips.com

Reminds me a bit of the Parallax Propeller chip.

TIL about the Parallax Propeller. Yes, it does seem very similar to the GreenArrays GA144, complete with an idiosyncratic language and IDE.

One distinction of the GreenArrays chip is that they claim it is very energy-efficient.

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