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(and if it is not apparent to some readers, most modern x86-based systems use 64 byte cache line sizes, which is sort of analogous to disk block size - quite a few memory operations tend to happen in 64 byte chunks under the covers - the ones that don't are "special")

To my knowledge all x86 based systems and ARM and Qualcomm designed chips all use 64 byte cache lines.

Apple's M2 uses 128-byte cache line.

Apparently these ~4k spikes are showing up only on AMD, and not on Intel, which is the one known to suffer from the 4k aliasing problem.

I wonder if it has to do with a non-ideal implementation of virtual address resolution for the next page.

Would you expect different performance with 2M page sizes? Is this a TLB issue or just a fundamental hardware issue?