For the traditional "100 nF per pin" problem, there is an actual constraint based solution. What you _really_ want is an impedance and cross-impedance constraint on current loops through power pins. That's, ultimately, what matters: not some rule of thumb, but actual physics that attempts to quantify the board's response to the chip's changing load.

Interestingly, Qualcomm actually gives you these, but I haven't seen many (any?) other chip manufacturers do that. I wish that'd became common practice.