Also arguably we already have 256 or 512 bit CPUs, what matters most for memory throughput is not the register width but essentialy the L1 cache line width (eg what in old CPUs was the databus width).

As for address width, we're not even close to get full 64 bit pointers from CPUs anyway, more like 48 or 52 bits.

Wide pointers (eg 128 bit general registers) would make sense for carrying capabilities for memory safety though I guess.