Didn't expect to see Verilog on the front page of HN.

1 nit pick, I think wherever you use a wire assignment you need the assign keyword. e.g

  wire [1:0] command = mem_out[7:6];
  wire [2:0] destination_addr = mem_out[6:3];
  wire [2:0] source_addr = mem_out[2:0];

should be

  assign wire [1:0] command = mem_out[7:6];
  assign wire [2:0] destination_addr = mem_out[6:3];
  assign wire [2:0] source_addr = mem_out[2:0];

Or maybe it's wire assign. I usually first declare the wire in a single statement then use assign on a new line.