I took a quick look at the IEEE 1800-2009 LRM (SystemVerilog, a proper superset of Verilog), and I can't see any BNF production that allows this. I think this is a case of iverilog being somewhat permissive.

In looking it up, I did come across the keyword "alias", which I was not familiar with, that effectively does what you've done here.

That said, it doesn't detract from an enjoyable tutorial. It's nice to see a little ASIC content on HN - duly upvoted!