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I think that has more to do with the amount you could get onto a die at that time, architecturally they had to move the MMU onboard first which left the cache(s) offboard

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It's more that they implemented it for higher speed as the split bus meant instruction fetches didn't block data fetches and vice versa - but it meant that without glue logic you turned a von neumann architecture into half-broken harvard one (because there's no support for copying data between the buses).

Some of the models had normal bus that didn't require unusual things like dual ported memory controller or other weirdness.

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