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That's only partially true - the GDDRX you'd find on say a 3090 is physically very different than what you'd find on a strix halo or mac or vanilla ram. e.g. runs 4 voltage levels not 2 so that it can transmit twice the info per cycle

Well, what they don't tell you about GDDR6X is that it's 4 voltage levels but it never goes from min to max or vice versa in a single transition (PAM4 MTA). It transfers 1.75 bits per cycle.

And then GDDR7 backed off to PAM3 and sends 1.5 bits per cycle.

There's a good chance [LP]DDR will use the same techniques once it gets into the same speed range.

Yes the cells are pretty much the same as they would be with hbm as well all the magic happens at the bus and the signaling, there is both a reason hbm and gddr have higher bandwidths and tradeoffs.

DDR has better latency hence the preference in CPU workloads where lower latency is more important due to variable workloads.

Very true, though traditionally it did refer to GDDR.