AI-assisted PCB design for KiCad 10
github.com
github.com
I have found the best results through a mix of Happy[0], this repo, and computer use to fill in the blanks.
It is _really_ good at the stackup and part config, but creates some absolutely terrible routes. It will snake tiny traces through some SMD pins even though there is plenty of space available outside of the component. When it hits an obstacle, instead of creating 2 45 degree turns, it does 10~30 small ones creating some sort of weird crooked arc.
I have produced a couple of boards for testing this way and they are generally functional.
I have tried KiCadRoutingTools[1] as well which does seem to create routes that make more sense.
Anyone any better experiences with these or similar tools?
[0] https://github.com/aklofas/kicad-happy [1] https://github.com/drandyhaas/KiCadRoutingTools
I did this months before that OpenAI demo, and produced a product that many people are using without knowing it was an AI designed PCB.
It ran using kicad completely headlessly from a terminal with a bit of python and DRC'd it in a loop until it passed. I sent it to PCBWay and it worked the first go. It did take a bit, but if you just set a goal and let 'er rip the LLM gets there in the end.
Would a real EE vomit if they looked at it? Maybe. Does it work? Absolutely.
However, capitalism demands it and we all have to compete. Look at the fortune 100. How many of those companies produce finely crafted artisanal hand-made things of beauty designed to last for 100 years and be passed on for generations?
The truth is that people say they want quality, and then buy the cheapest thing they can find that works for today. It has always been, and will always be this way... At least until/unless we find ourselves in Treks post-scarcity, fully-automated, luxury communism.
In the meantime I try to apply my limited time on earth as effectively as I can, but putting the most work into the place where it will do the most good.
In terms of result quality, I would say that the results are distinctly "2024/2025 LLM programming quality". The models lack a certain... taste? Good and careful prompting can help, but for example "use hierarchical sheets" can yield a single hierarchical sheet containing 3 copies of the same thing instead of three instances of a hierarchical sheet containing the same thing once. When pointed out, the model can of course do it no problem the way you want.
Why don't you make it a part of the system prompt then?
Nothing: Opus plops down everything into one big schematic sheet
"Use hierarchical sheets!": Opus uses them but does not realize they can be multi-instanced
"...":
It would probably be well worth to optimize this on synthetic projects, but realistically we are small shop, our required PCB-design output is not that masive, and I expect Opus 5.8 to just do the correct thing automatically as its being RLHFed on these tasks as we speak :)
I’d say that at the moment it still requires you to look at its results and point out their weaknesses and/or route a couple of traces yourself and then hand it back.
This project from a couple of weeks ago is a great example. I’m new to ST MCUs: in addition to the PCB, Claude brought up the firmware and driver. https://github.com/ckemere/hub-imu
I did find LLMs to be very effective on answering questions about routing, part selection, and identifying problems; was using a new MCU (Atmosic) with some unusual power circuitry, and got a working board first go. LLMs also crushed getting it working with rust (Very likely I am the first person to program an Atmosic MCU in rust); found a debugger that would work (NXP MCU-Link; the St-Linkv3s I normally use won't work for this, and the official recommended part is very expensive). The LLMs wrote a probe-RS configuration for it, linking scripts etc.
The LLMs also, under close direction, wrote a minimal HAL subset for I2C, SPI, power management, clocks, and BLE. I pointed it to my STM32 HAL as an API guide, set up the basic data structures, and pointed it to the Atmosic SDK (In C). It connected the dots, and produced a working HAL with a familiar API.
I had Fable work on it, and it made a good board, after some trial and error. I used mixtelas previous MCP tool, and even had it do ngspice runs on the filters. One of the tricks was to run a "tournament" style system for routing and lock in good routes. It also seemed to have and idea of what a "good" board should be.
And it found all the components on jlcpcb, made sure they met specs, gave me options, etc. and it outputs everything I need to upload the boards and get them produced.
I've tried with Opus, and Opus doesn't quite get to what I would consider a "good" board, but it will get you close.
I haven't ordered the board yet (cost plus being cautious) but looking over it, I've yet to find any issues on it. I just ordered a simple connector board all done by AI last night with a few resistors and caps on it, all to be assembled by jlcpcb. Obviously, looking over it, I thought it was good enough to spend $60 on. We shall see.
But like so much in AI, it helps if you have some domain knowledge. I'm not sure how it'd go if I just had a newbie vibe code a board. I help with FabAcademy, and I fully expect to see this done many times there, over the next year.
I use Backplane more for overall "acceleration" of hardware vs. proompt -> product stuff (this is still mostly slop imo)
Programmers: code always was the easy part, being relied upon is the hard part / architecture / aligning stakeholders Mathematicians: proving theorems was never like the important part, it’s “understanding” (without tangible output of any kind) Lawyers: well actually I don’t do anything besides being “accountable” Lab technicians: well actually I’m just logging what the robots did
And then “.. and a chatbot can’t do that!”.
Very interesting indeed.
The component selection through JLCPCB saves so much time - best part, if a component is out of stock, Fable quickly redesigns and reroutes to board for a part that is in stock (if the footprint is different)
It’s not perfect, but months worth of work gets done in hours.
Which models did you use and what was your rough process? I had better luck with Astra for this...
Or do you need to get an API key first?
Seems to be scraped data? and then you review it manually like it recommends in: https://github.com/mixelpixx/Konnect/blob/9488e5f09717cb508c...
It's a pity JLCPCB always wants to nudge me towards their own EDA tools.
Perhaps someone can vibe-code an LCSC interface that uses a headless browser?
Claude helped me cut my BOM costs on JLCPCB/LCSC significantly by suggesting cheaper versions of the parts I was already using.
It also designed a new board for me for KiCad 10 (a brand new project), including all parts selection from JLCPCB.
I ended up not using JLCPCB for the PCBA, I only ordered blank PCBs from JLCPCB because cost of PCBA was too high for this project, so I had Claude redesign the schematic to use through-hole parts that I will assemble myself. I was able to source all the parts from Mouser and Amazon.
Enter what you are searching for at the top of the page, the results are at the bottom of the page. In between are categories that can be turned on and off.
They are using the latest JLC API.
I recently asked Claude (Opus 5.5) to design a wifi fan speed controller based on the ESP32 microcontroller. I told it to design a circuit for KiCad 10. I told it to write the software based on the ESP-IDF framework (for ESP32). I told it I would design the PCB based on the schematic it created.
It went to work. About 15 or 20 minutes later, it was done.
Everything looked good. Parts selection was reasonable. The first schematic was kind of weird, every part was placed on its own without any interconnected lines, so I had it re-do the schematic to show the part interconnections. It did a pretty good job.
Then I went to work designing the PCB. I had to find a project case and gave Claude some JPG images from the amazon page of the case dimensions, and it created a perfect PCB outline complete with mounting holes for the PCB.
I designed the PCB, but it's been a while since I did anything with mains voltage (120v here in the US). I asked Claude to analyze my PCB design, and it pointed out some issues with my trace routing, like not putting low-voltage traces crossing high-voltage traces, etc.
I then directed Claude to design its own PCB based on the project case constraints, and it did a fantastic job - way better than I did, honestly. It separated all the high voltage areas of the circuit from the low voltage areas, and clearly marked them with warnings on the silk screen.
I had it do all the part selection, and I purchased the parts - I'm not giving it my credit card to order parts, I can still do something useful towards this project.
I did not have to install anything for Claude to do any of this, it installed whatever tool it needed, and it generated the KiCad files.
So, this seems like PCB design is "solved".
Claude also wrote all the software for the ESP32 in another folder, including a web-based interface to control fan speed.
The PCBs and parts are on their way to me now. I guess I'll find out in about a week how "solved" this really is, but looking at the PCB design, it's looking really good.
Now it probably helps that I have 40 years experience doing exactly these tasks, so I can tell when something is going to work or not, and I know how to tell Claude what I want. Someone new to circuit/PCB design might have a more difficult time because you don't know what you don't know. I was very specific about the kind of circuit and parts I wanted - an ESP32 controlling a Triac controlling mains voltage with an optocoupler, etc - this is something I've built myself decades ago, so I already knew what "solved" looks like.
I have some friends who work on designing wafers and they told me compared to autorouting, hand layout is always better, with quality asymptotically approaching a certain ideal with hours invested.
Based on how many engineer-hours you can put in, you can get a single or even double digit increase in silicon density, it's just that nobody actually has the manpower to actually get close to that ideal, but the difference is very noticeable between 'tier 1' and 'tier 2' manufacturers, the former of which can afford an army of highly educated engineers who will slog through this task, with the latter having to decide where to spend the effort.
This is one of the reasons why second or third generations of CPU architectures perform better even on the same or very similar process node, because this logic optimization builds up.