Why are chip companies allergic to open source?
zeroasic.com
zeroasic.com
They have automated a lot of the really hard work and most the industry is trained on their tools.
Open source tools could grow the market by letting many more creators afford to make designs, effectively commoditizing the manufacturers complement.
The reason for their quasi-monopoly is the one stated by another poster, that the 3 big EDA companies have privileged relationships with TSMC and the other major foundries so they have access to information that is not available to anyone who would want to develop alternative EDA tools for state-of-the-art CMOS processes and not for ancient processes down to "28-nm" (i.e. at the level reached in 2011, 15 years ago).
We will eventually reach a point where shrinking transistors provides diminishing returns, which should give open-source tooling and processes more time to close the gap. But we're probably still at least a decade away from seeing how that plays out, and who knows what happens with quantum computing, new materials, 3D integration, or some other semiconductor breakthrough in the meantime.
Even then, I don't think open source necessarily catches the absolute state of the art. Unless a startup fab decides to build its own EDA stack and open-source it as a way to attract customers, there will probably always be some gap between open and commercial tooling. The question is whether that gap eventually stops mattering for most designs
An excellent insight -- good tooling could be a differentiator for a US fab looking to compete on something besides price.
Open source would always be behind, the fabs don't want other fabs knowing about their process which is why its secluded behind the EDA tools with NDAs.
I use the open source EDA tools for VLSI everyday and I do like them, especially how hackable they are, but they are very unreliable compared to the closed source tools, and that's not the highest bar.
Run time of the open source EDA tools are also very slow for designs over, say, ~250K gates. And that's an issue when in commercial designs the base unit for measuring the number of gates in a macro is megacells, i.e. 10^6 cells. Much of the effort of the commercial tools has just been keeping up with Moore's law which is not easy when many brute-force form EDA algorithms are like n^3 even with heuristics.
I mean you can download and use verilator, openroad, yosys, ngspice, bsim-cmg, klayout and all this fun stuff.
The big blocker is really pdks. Where are you gonna get something that actually fabs? ASAP7 is just predictive.
And foundries are incredibly geopolitically important so they aint revealing anything.