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Comment by mk_stjames | Hacker News Reader

I'm trying to figure out the video part, there is a demo screen that is showing pretty high res in color, and this says 1024x600 and 256 colours- that is mighty impressive for a 6502, that is driving way more pixels that I ever saw in that era, so I was expecting there was some other chip being used as a screen buffer and graphics chip...

but it looks like the LCD has to be bit banged by the CPU data bus directly? I see the 8 bit data bus is going straight to the LCD thru a buffer IC.

I don't see where in the memory map there would even be enough space for a screen buffer that large to be located, so I take it you have to write you own graphics handling yourself and pick a spot in memory for it all?

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It seems based on previous entries that the display connector goes to a smart LCD controller, RA8889: https://www.maddox.pro/?p=429

A description (from https://www.raio.com.tw/en/RA8889.html):

> RA8889 is a low power TFT controller with powerful display functions and build-in internal SDRAM memory. In order to quickly refresh the screen content with the display memory, RA8889 provides not only parallel, 8080/6800 8/16-bit MCU interface, but also 3/4 wire SPI and IIC serial interface. Plenty powerful functions are provides from RA8889, such as multiple display buffers, Picture-in-Picture, transparency control, display with rotation & mirror, and build-in JPEG and AVI decoder.

I wondered the same thing, and it looks like it uses this CMOS-compatible high level TFT driver: https://www.raio.com.tw/en/RA8889.html with a character generator, geometry primitives, etc.

> this says 1024x600 and 256 colours

> I don't see where in the memory map there would even be enough space for a screen buffer that large to be located

1024 × 600 with 256 colours is 600 kB. Even in monochrome, it would be over 64 kB.

> but it looks like the LCD has to be bit banged by the CPU data bus directly?

Even at 20 Hz, that would involve writing over a ten million pixels per second, giving you about 1 CPU cycle per pixel ⇒ there’s no way to do that with this CPU.

The modern WDC 65C02 is also way faster (up to 14MHz in the right conditions) than other 6502s of the era (usually 1-2MHz).

These sorts of project should be using the 68000 or the 65816 which both give a 24 bit address bus. Meaning they get 16 MB of address space to work with. They can make directly addressable frame buffers at high resolutions and reasonable color depths, and still have lots of memory available for programs and data.

At that point you may as well go for a RISC-V or ARM microcontroller.

I'm guessing that that is just the spec for the hardware, not what the machine can actually use.

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