V100 SXM2 pinout and NVLink reference
github.com
github.com
I did this manually back in Feb 2024[1], but only got "connector A" mapped out and a partially designed SXM2-to-PCIe interposer designed before getting distracted.
During the process, I discovered Facebook's Big Basin JBOG schematics/specs (from Open Compute), which contained a design derived from NVIDIA's DGX-1 reference implementation. Looks like this clears up some gaps in the current reference. It also explains some of the design choices, like the form factor and similar pinout to OpenPOWER.
https://docs.google.com/spreadsheets/d/1DfH0T9KWWoc2CpKZsRIT...
If you’re still getting poor performance, point an Astra agent at it and ask it to benchmark and find the pressure points.
Also speculative decoding has changed the game completely. I’ve managed to 2-3x’d the theoretical max for my setup. Apple Silicon is a bit more limited here, and cannot deal with large DFlash block sizes. But AMD and Intel chips are game.
Good luck and godspeed!
I have a brain damaged quant of DeepSeek V4.1 (IQ2_XXS) running at about 80-100 t/s and 950 pps. It’s really not that bad, but not as smart as the full model. I have Qwen Flash Next 3.8 on UD4 K XL at about 200 t/s single, 450-550 aggregate t/s and 3-4k pps. Hard to say which is smarter honestly between the two models.
It’s a great model for local LLM. I wrote my own engine and I havent seem any 4 card benchmarks faster than it yet so these cards definitely have more ceiling than most people thought a few months ago. They don’t have a lot of compute but they have just enough to keep their VRAM busy most of the time :)